A social robot has to ascertain the personality of the human interacting with it through verbal or non-verbal communication. While existing literature focuses on facial feature recognition for non-verbal communication, we propose using handshake patterns to classify the personality of the concerned human. Due to the largely random nature of the gestures in handshakes, general pattern recognition methods cannot be used to classify them effectively. This paper proposes to classify a handshake into two labels: dominant and submissive, by using the K-Nearest Neighbor algorithm on apriori ranked statistical markers extracted from the training data. For the purpose of data acquisition, a wearable device attached to the wrist of the robot was designed. The wearable was fitted with a 9-axis accelerometer and a flex sensor. The training data consists of accelerometric data from handshakes with 12 different individuals, with each individual exhibiting both a dominant and submissive personality trait. Mutual Information and Statistical Dependence are used to rank statistical markers extracted from the training data. The best ranked features were used to classify the handshakes using K-Nearest Neighbor algorithm and classify the handshake into the two class labels. The proposed methodology classifies data with an accuracy of 75.0% when tested on 8 different handshakes.

Read-Modify-Write (RMW) instructions are widely used as the building blocks of a variety of higher level synchronization constructs, including locks, barriers, and lock-free data structures. Unfortunately, they are expensive in architectures such as x86 and SPARC which enforce (variants of) Total-Store-Order (TSO). A key reason is that RMWs in these architectures are ordered like a memory barrier, incurring the cost of a write-buffer drain in the critical path. Such strong ordering semantics are dictated by the requirements of the strict atomicity definition (type-1) that existing TSO RMWs use. Programmers often do not need such strong semantics. Besides, weakening the atomicity definition of TSO RMWs, would also weaken their ordering -- thereby leading to more efficient hardware implementations.

Although the sequential consistency (SC) model is the most intuitive, processor designers often choose to support relaxed memory consistency models for higher performance. This is because SC implementations that match the performance of relaxed memory models require post-retirement speculation and its associated hardware costs. In this paper we propose an efficient approach for enforcing SC without requiring post-retirement speculation. While prior SC implementations guarantee SC by explicitly completing memory operations within a processor in program order, we guarantee SC by completing conflicting memory operations, within and across processors, in an order that is consistent with the program order. More specifically, we identify those conflicting memory operations whose ordering is critical for the maintenance of SC and explicitly order them. This allows us to safely (non-speculatively) complete memory operations past pending writes, thus reducing memory ordering stalls. Our experiments with SPLASH-2 programs show that SC can be achieved efficiently, with performance comparable to RMO (relaxed memory order).