This paper presents a fractional-N all digital phase locked loop (ADPLL) based on a new quad-core class-F3oscillator, which reduces the out-of-band phase noise of ADPLL. The LC tank of the proposed oscillator incorporates both parallel and series resonant cavities compactly. It increases an additional impedance peak around the third-harmonic of the fundamental oscillation voltage, thus enforcing a pseudo-square voltage waveform around the LC tank. Consequently, the effective impulse sensitivity function (ISF) decreases, thereby reducing the phase noise. Furthermore, the proposed topology demonstrates low phase noise penalty during multi-core resonance. The ADPLL is implemented in a 40nm CMOS process. The simulated phase noise of the quad-core class-F3oscillator at 1MHz offset varies from -124.5 to -126.1dBc/Hz depending on the output frequency, which ranges from 10.29 to 12.75GHz. The oscillator consumes 24.36mW from the supply and exhibits a figure-of-merit (FoM) of 192.5dBc/Hz. Ultimately, the ADPLL utilizing the proposed oscillator exhibits an excellent RMS jitter of 49.7fs and achieves a FoM of -250.5dB.

This paper describes a 4T4R ultra-wideband transceiver (UWB TRX) with compact baseband shifter and digital phase interpolar (DPI) for beamforming to alleviate the contradiction between power consumption and performance. A complementary stacked multi-supply switched-capacitor power amplifier (SCPA) is introduced for efficiency. It allows PA work in both high output and low output mode, which makes the proposed transceiver could work as traditional short-ranging communication and ranging UWB TRX or as a 4 elements beamforming TRX for better system efficiency and sensitivity. A bounding wire based in-chip inductor less matching network is adopted for wide band and farther reducing the chip area. Implemented in 22nm CMOS technology, the proposed TRX works from 3GHz to 10GHz, achieve 3.7–4.2 dB NF and 57.1%@11.8dBm / 48%@-0.23dBm drain efficiency, occupies 8.72mW for RX and 31.9mW / 9.6mW for TX per channel.

This paper presents a broadband 18-33GHz receiver (RX) front-end with a core area of only 0.12mm2. In the local oscillator (LO) generators, a compact edge-combining (EC)-based frequency multiplication scheme is proposed to generate wideband and precise in-phase and quadrature (I/Q) LO signals at millimeter-wave frequencies. In the output stage of the LO chain, the switched-capacitor (SC) XOR modules triple the output clock frequency through edge-combining, which provides a 3× frequency reduction for the global clock distribution. The clock tripling is independently performed in I/Q differential LO signals, and the orthogonality of LO signals is not influenced by frequency multiplication. Implemented in TSMC 40nm GP CMOS, the proposed receiver core occupies only 0.46mm × 0.26mm. The RX front-end achieves a conversion gain of 42dB, a Noise Figure of 5.6dB, a baseband bandwidth of 100MHz, and an IQ phase variation < 1.3° (1σ interval, without calibration), while operating in the K/Ka band at 18-33GHz.

Backscatter transceivers are often used in ultra-low-power Internet of Things (IoT) applications. However traditional backscatter transceiver (TRX) cannot actively control the transmitted power, which greatly limits the communication distance. This paper introduces a novel backscatter TRX operating in the ultra-high frequency (UHF) band, with a low power consumption of only 136μW and an impressive communication range surpassing 800 meters. Unlike the backscatter, the received continuous wave (CW) is not reflected via impedance modulating at the antenna but is directed into the TRX to be modulated and amplified. This technique significantly extends the communication range at a low power consumption. A coupler serves to prevent the direct entry of transmitted signals into the receiving path, ensuring the received CW remains unaffected to be modulated. Implemented in TSMC 40nm CMOS, the proposed TRX core occupies 0.7 mm2and works under a 0.7V supply voltage with the -54.6dBm input power and -20dBm output power.

A 2-T Antifuse cell with only thin-oxide transistors is proposed in this work, which is completely compatible with standard CMOS process. Its layout area is only as 0.5 μm2(1×0.5 μm2) in 40nm CMOS process, representing a 67% reduction in size compared with previous work at the same thickness. Considering the bitcell trade-off between area and reliability, the reliability is enhanced by an auto shut-off program logic and its feasibility is proven. Moreover, based on the cell, a 4Kb OTP array simulation shows that the program current is only 7 μA and read current is 5 μA. The characteristics of the memory array demonstrate its suitability for low-power applications in systems like RFID.

This paper presents a fractional-N all digital phase locked loop (ADPLL) based on a low in-band phase noise switched-capacitor digital phase interpolator (SC-DPI), which reduced the in-band phase noise of ADPLL. The SC-DPI utilized a capacitance vector-sum structure with a short signal chain to improve the in-band phase noise performance. Designed in 40-nm CMOS technology, from simulation results, the proposed SC-DPI worked at 1GHz and achieved -126.2 dBc/Hz in-band phase noise at 1kHz and -142.6 dBc/Hz at 1MHz. The proposed 8GHz ADPLL based on SC-DPI achieved -110.5 dBc/Hz and -117.2 dBc/Hz in-band phase noise at 1kHz and 10kHz respectively.

This paper presents a design of 250MHz single-ended digital transmitter (DTX) with switched-capacitor power amplifier (SCPA) for communication between mobile phones and satellites. The implementation of SCPA enhances linearity and efficiency. For compact die area and high efficiency, 50%-duty-cycled clocks are used in the DTX eliminating second-order harmonic without differential architecture. Aiming at higher efficiency compared to conventional quadrature DTX, the technique of digital-domain in-phase (I) and quadrature phase (Q) cell sharing is applied in this work. Moreover, the combination of three signals with specific amplitude and phase eliminates third-order harmonic, improving the output spectrum significantly. The DTX is designed in 22nm standard CMOS process and reaches a peak output power of 8.87dBm at 250MHz and power-added efficiencies (PAE) of 57.4%. When modulating a 4 MHz 64-QAM signal, the error vector magnitude (EVM) is 0.61%, while the average output power and PAE are 1.93dBm and 32.9%, respectively.

This paper presents a 2.85-mm2 0.4-6 GHz RF transceiver in 40-nm CMOS for low-cost and low-power IoT micro-hub applications. A single-path receiver (RX), an all-digital phase-locked loop (ADPLL), and a digital transmitter (DTX) (including a digital power amplifier, DPA) are integrated. In the RX, to reduce the chip area and power consumption, an inductor-less capacitive-feedforward wideband LNA and a Gm-C filter-based dc offset cancellation (Gm-C-DCOC) technique are proposed. The RX achieves a noise figure (NF) of 1.3-4.9 dB over 0.4-6 GHz while consuming 31 mW. The measured average IIP3, in-band P1dB, and calibrated IIP2 of the receiver are 4.5 dBm, −13.8 dBm, and 67.5 dBm, respectively. In the ADPLL, a calibration-free retiming fractional frequency dividing (FFD) scheme based on a parasitic insensitive digital phase interpolator is adopted, for releasing the narrow loop bandwidth limitation and achieving better phase noise without active noise cancellation techniques. In the DTX design, a piecewise bias voltage (PBV) technique is proposed for the AM-AM linearization. It achieves a peak output power of 22.5 dBm at 840 MHz with a drain efficiency of 60.2%. The DPA can work in a high-power mode without PBV and a middle-power mode with PBV for modulation with different complexity. Thanks to PBV, the DTX achieves 5.9%, 5.3% EVM for 2MS/s 16-QAM and 64-QAM without digital pre-distortion (DPD), respectively. The designed broadband reconfigurable transceiver can support most of the common IoT protocols in most key metrics.

A Gm-compensated 46-101 GHz broadband power amplifier (PA) for high-resolution FMCW radars is presented in this paper. For bandwidth (BW) expanding, a Gm compensator-based negative feedback chain is applied to the PA, compensating the large gain ripple caused by a high-k transformer (TF)-based ultra-wideband interstage matching network (IMN). Based on the proposed Gm-compensated technique, a flat and ultra-wideband power gain of the PA can be obtained with the high-k TF-based IMN. The proposed PA achieves a 55-GHz BW without additional area overhead and efficiency loss. 74.8% of the fractional BW is obtained with2.

A Quadrature/Polar hybrid digital transmitter architecture (HB-TX) is proposed in this paper, which consists of a main digital power amplifier (DPA), an auxiliary DPA, and a low-bit phase selector. In the proposed HB-TX, coarse polar modulation is realized by combining the main DPA and a low-bit selector, while a fine quadrature modulation is realized by the asymmetrical quadrature recombination of main and auxiliary DPAs in a small range. Through coarse and fine modulation, the HB-TX realizes fast signal modulation and does not require high-speed and high-resolution phase modulator. With the coarse polar modulation, the HB-TX achieves high efficiency which is close to that of polar transmitter and no longer suffers from 3 dB back-off. Since the asymmetry of two-path DPA arrays improves the isolation between two channels, local oscillators (LOs) with 50% duty cycle is employed to further improve the HB-TX's efficiency. Simulation results show that the HB-TX with a 4-bit selector achieves 23.7-dBm peak output power with 39.2% peak power added efficiency (PAE). When modulating a 64-QAM signal with 80-Msym/s symbol rate and 6.5-dB peak average power rate (PAPR), the HB-TX improves the average drain efficiency from 16.3% (achieved in quadrature transmitter) to 22.2% The average output power that is delivered by the HB-TX is 17.6-dBm with 17.4% average PAE, while the error vector magnitude (EVM) is -35.87 dB.

An 81-99 GHz tripler for wireless transceiver LO generation is presented in this paper. To suppress the fundamental signal and enhance the 3rd harmonic, the inversion signal is applied to the gate of the cascading transistor of the push-push differential pair. A capacitor is connected to the source and drain of the cascading transistor to further suppress the fundamental signal. Without additional filters, the tripler achieves more than 40 dBc of fundamental suppression with an even harmonic suppression of up to 60 dBc. The tripler reaches an output power of -2.6 dBm (4-dBm input) at 91.5 GHz with a 20% bandwidth of from 81 to 99 GHz. The core area of the chip occupies only 190 μm×530 μm in TSMC 40-nm CMOS process and consumes 28.2 mW.

This paper presents a fractional-N all digital phase locked loop (ADPLL) using a retiming high linear digital phase interpolator (DPI), which is free from pre- and background-calibration. The DPI utilizes a charge-sharing effect insensitive charge-based structure to improve the linearity. Designed in a 40-nm CMOS technology, the proposed DPI achieves 9-bit resolution, 0.3ps integral nonlinearity (INL) and 0.083ps differential nonlinearity (DNL). The proposed ADPLL achieves −118 dBc/Hz in-band phase noise at 1MHz and −93.9dBc fractional spur with the 0.3ps nonlinearity of DPI.

In wearable biomedical applications, a constant dc common-mode (CM) voltage of low-pass filters (LPFs) is needed to boost the dynamic range when low supply voltage is used for high power efficiency. Traditional source-follower based LPFs consume very low power but introduce a CM voltage difference between input and output. This paper presents an ultra-low-power LPF, which features a source-follower based topology with a bulk-feedback technique. The bulk-feedback technique is proposed to keep a constant dc CM voltage, which is robust to process and temperature variations. In order to validate the proposed concept, a fourth-order LPF has been designed as a prototype. Implemented in a TSMC 180 nm CMOS process, the filter occupies an active area of only 0.048 mm2. Simulation results show that the filter consumes 9.0-nW static power from a 0.5-V voltage supply when the cutoff frequency is set to about 200 Hz. The filter achieves an input-referred noise in -3 dB bandwidth of 41.21 μVrms and an in-band IIP3 of 4.0 dBV, which corresponds to a spurious free dynamic range (SFDR) of 61.1 dB. The proposed LPF achieves a competitive FOM among the reported works.

This paper presents an 8-bit calibration-free LO-path phase shifter (PS) for large scale 28 GHz phased-array transceiver. To overcome the nonlinearity of a vector-summing PS, two 8-bit digitally-controlled variable gain amplifier are utilized to generate high linearity amplitude modulation. Three transformers cooperating with a parallel resonator are developed to sum the I/Q signal as well as provide a fine isolation between I/Q path, thus provide a high linearity vector summation. Simulation results show that the PS achieves 360° phase shift with 8-bit resolution and a RMS phase error of 0.51°. The INL and DNL of phase-shifting is +0.66°/-0.83° and +0.22°/-0.19° respectively. Implemented in TSMC 40 nm LP process, the chip occupies an active area of 0.18 mm2and consumes 28.6 mW from 1.1 V supply voltage.

This paper proposes a 2.4 GHz ultra-low power pseudo-backscatter modulator with an integrated directional coupler for wireless sensor network applications. In order to improve the performance of backscatter modulator for multilevel modulation, an integrated directional coupler is employed to isolate the radio frequency carrier wave from the modulated signal. As a result, the carrier wave can be modulated in radio frequency domain independently without being affected by reflection coefficient of a conventional backscatter modulator. For further reducing power dissipation, the modulator only employs buffers for output and implements modulation by passive circuits. The proposed modulator is demonstrated in a standard 40 nm CMOS 1P10M process and it achieves 64-QAM modulation at 3 Mb/s data rate by consuming only 43.2 μW with a supply voltage of 0.8 V.

A 12-bit 2.5GHz digital-to-time converter (DTC) for high resolution and high linearity applications is presented in this paper. The DTC is segmented into a 4-bit coarse stage and an 8-bit fine stage. The proposed fine stage utilizes parasitic-insensitive charge-based (PICB) phase interpolator (PI) with significant improvement in linearity. The PICB PI outputs 50% duty cycle differential clock and its performance is insensitive to parasitic effect. The DTC is designed in 40nm CMOS technology and consumes 7.1mW with a 1.1-V supply voltage. Simulation results show that the peak integral nonlinearity and differential nonlinearity are 0.37ps and 0.085ps, respectively.

This paper presents a low power SAW-less 2.4-GHz receiver for short-range communications. To ensure sufficient out-of-band (OOB) linearity for SoC existence, a LC matched series N-path filter based receiver topology is proposed. The radio frequency input is followed by the LC matched series N-path filter, which provides sufficient ultimate rejection when consuming less power than conventional N-path filters. An on-chip inductor and a capacitor are utilized to achieve input matching and improve the NF. Implemented in TSMC 40nm LP process, the chip occupies an active area of 0.312 mm2. Simulation results show that the receiver consumes 2.2 mW from 1.1V supply voltage with a NF of 6.3 dB (with the on-chip inductor) and a voltage gain of 38.4 dB. The baseband achieves a third order filtering response with 1.5 MHz bandwidth. The OOB 1-dB compression point is +7 dBm and the OOB IIP3 is +22 dBm.

This paper presents a digital phase noise cancelling scheme for ring oscillator (RO)-based fractional-N ADPLL, which can suppress both in-band and out-of-band phase noise of RO. The scheme adopts a high-resolution time-to-digital convertor (TDC) to sample the rising edge timing errors between RO output and the reference signal (REF) and a matched digital-to-time convertor (DTC) to compensate these timing errors to align RO output with each rising edge of REF, eliminating the phase noise of RO output. To get accurate phase noise cancelling, it is essential to realize high resolution and good match between TDC and DTC. These two modules are implemented in 40 nm CMOS with 2 ps resolution and 8.34% mismatch. System-level simulation results show that, the in-band phase noise at 1 MHz offset can be cancelled by the level of 20 dB and the out-of-band phase noise at 10 MHz offset can be cancelled by 10 dB, with the 200 MHz reference signal.

This paper presents a MICS/ISM band receiver for ultra-low-power applications with a passive RF front-end. A shunt passive mixer along with low input capacitance amplifiers is introduced to decrease the large load capacitor and minimize power consumption of the Local Oscillator (LO) buffers without significant noise figure (NF) degradation. Measurement results show that the receiver consumes 89 μW from 1 V supply voltage with a NF of 7.5 dB and a voltage gain of 47.6 dB. S112.

This paper proposes a DC-DC buck converter with all-pass network based passive level shifter in 55nm standard CMOS process, for battery powered portable applications. In order to handle high battery voltages in this advanced standard CMOS process, a passive level shifter based on all-pass network is applied for gate oxide protection. Drain extension is proposed to obtain high breakdown voltage of active region. The proposed buck converter with the passive level shifter works in DCM operation as its load current varies from 0.1-10mA. The buck converter achieves a peak efficiency of 93.7% and 83.8% at 10mA load current, with a supply voltage of 1.8V and 3.7V, respectively.

This paper presents a temperature and supply voltage variation-tolerant CMOS relaxation oscillator which is suitable for ultra-low power systems. A low-power low-cost half-period pre-charge compensation scheme is proposed to eliminate influences of the delay of the comparator and the RS latch on the frequency stability of the relaxation oscillator. In a clock period consisting of four working stages including normal charge, discharge, pre-charge and hold stage, the threshold voltage of comparators is adjusted dynamically. A 32.7-kHz relaxation oscillator with the proposed half-period pre-charge compensation scheme is implemented in a TSMC 0.18-μm CMOS process, occupying a silicon area of 0.048 mm2. Simulation results show that the proposed relaxation oscillator consumes 51-nW at room temperature from 0.6-V power supply, and temperature stability of 43.1 ppm/°C from -55 °C to 125 °C and ±0.60% frequency variation with supply voltage from 0.5 V to 1.0 V are achieved.

This paper presents a 0.5-2GHz RF front-end with Series N-path Filter. With series 8-path filter applied, an ultimate rejection larger than 46 dB with 30 dB out-of-band rejection at 50 MHz offset is achieved. Dynamic power consumption is saved due to small filter switch size compared with parallel structures. Utilizing a tunable narrow band LNA in front of series N-path filter, 3rdharmonic rejection exceeding 54 dB with robust to process variation is realized. These techniques improve the front-end's adjacent and far-end frequency selectivity in RF domain, relaxing mixer's linearity design pressure. Implemented in 65 nm CMOS process, the frontend achieves a NF of 2.6-5.7 dB and maximum gain of 46-60 dB at 0.5-2 GHz, consuming 18-26 mW from 1.2 V voltage supply and occupies an area of 0.56 mm2.

A novel human body channel (HBC) energy harvesting scheme for body sensor networks (BSNs) is proposed in this paper. Human body channel is utilized innovatively as energy transmission medium to reduce the transmission loss dramatically and eliminate influence of shadow effect. Further, a high sensitivity and efficiency rectifier is presented by introducing an effective threshold compensation circuit. Experimental results of the energy harvesting scheme show that it can supply 2-μW power typically at -5 dBm transmitted power and up to 19.5-μW at +7 dBm transmitted power by 30 cm distance of human body channel. The sensitivity of the proposed rectifier is -22.5 dBm with 1-V output voltage. When offering 5-μA output current, the rectifier can achieve 25.87% efficiency. The rectifier is implemented in a standard 0.18-μm CMOS process and operating frequency is 145 MHz.

A wide band radio frequency (RF) root-mean-square (RMS) power detector (PD) is presented in this paper. A CMOS rectifier with unbalanced source-coupled pairs and auxiliary capacitors is utilized to constitute the reverse received signal strength indicator (reverse-RSSI) architecture as proposed power detector with operating frequency from 300 MHz to 10 GHz. The auxiliary capacitors are introduced to improve linearity at high input power dramatically. The power detector can be connected to power amplifier without directional coupler due to the capacitor attenuation array. Simulation results show that the maximum detection power is as high as +30 dBm and dynamic range reaches more than 42 dB with ±1 dB error. The proposed power detector is implemented in a standard 180nm CMOS process with 0.113 mm2core area. The supply voltage is 3.3 V, and its static power consumption is 0.55 mW.

A novel architecture of high frequency resolution LC-tank based digitally controlled oscillator (DCO) is presented in this paper. The proposed architecture utilizes a differential tapped inductor and a capacitor array within the taps for fine frequency tuning. A prototype of 1.6 GHz DCO integrated in 0.18-μm CMOS technology exhibits a tuning range of 40.2% and a phase noise of -123.6 dBc/Hz@1MHz. With a minimal capacitance step of 7.5 fF, the frequency resolution is improved to 7.6 kHz/LSB. The DCO dissipates 3.2 mA from a 1.8 V supply and occupies an area of 0.46 mm2.

This paper presents a 65 nm SAW-less receiver front-end. Using 3-phase clocks for impedance translation, an RF filter with 3rdorder harmonic rejection is obtained. Employing this filter as the front-end's input matching network and a two-stage low noise amplifier's load, a 3rdorder RF filter is realized. In addition, by using 3-phase 1/3-duty-cycle LO, a 3rdorder harmonic rejection mixer is realized. The mixer's harmonic rejection ratio is less sensitive to gain and phase error compared to conventional 8-phase mixers, since the 3-path's gain ratio is 1∶2∶1. These two techniques enhance 3rdorder harmonic rejection ratio to 80 dB in case of 6% duty-cycle error, 2% gain error and 0.5° phase error. The front-end achieves a noise figure of 3–6 dB from 0.5 GHz to 2.5 GHz, consumes 21–33 mW power from a 1.2 V voltage supply and occupies an area of 0.35 mm2.

This paper presents a low TX noise transmitter with digital modulated power amplifier (DPA) for UHF RFID reader System-on-Chip. With I/Q digital signals directly modulated on DPA, the transmitter eliminates the pulse shaping filter, up-conversion mixer and power amplifier driver, which are dominant noise contributors in a conventional RFID transmitter. A switch-mode power amplifier cell is adopted in the DPA, which suppresses the amplitude noise in the TX chain. An LO signal buffer strategy is proposed to minimize uncorrelated phase noise which cannot be cancelled by self-cancellation in the RFID receiver. A low noise self-adaptive LDO is designed for lowering TX noise and stable output power. The transmitter achieves a TX noise density lower than -145dBc/Hz and provides a peak output power of 24 dBm with 48% drain efficiency when transmitting CW signal. Through pre-distortion, the transmitter can achieve a spectrum mask with -50 dBc for ACPR1, -62 dBc for ACPR2 and -65dBc for ACPR3. The proposed transmitter is fabricated in a standard 0.18-μm CMOS process with an area of 1000×640μm2.

This paper presents a SAW-less GNSS front-end amplifier with GSM blocker suppression using CMOS directional coupler notch filter. The front-end amplifier is aimed at the GNSS receiver integrated in cellular phones. Based on our proposed CMOS stacked spiral-coupled (SSC) directional coupler working at the frequency of 900MHz as notch filter, the front end amplifier achieves a NF of 1.7dB and a 80.4-dB suppression of the GSM blocker while provides signal gain of 38.6-dB for the GPS L1-band signal.

This paper presents a SAW-less 0.2-3GHz front-end with high out-of-band linearity. Modified impedance translation technique based on N-path current driven mixer is used to improve out-of-band IIP3. At the input node, an 8-path passive mixer switched by 8-phase clocks at the frequency of fLO/2 is utilized to achieve impedance match at fLOand filter out-of-band interferes, while contribute negligible noise. Using a 4-path mixer as the LNA load, switched by 4-phase clocks at the frequency of fLO, out-of-band interferes is further attenuated. Implemented in 65nm CMOS process, the proposed front-end aiming at reconfigurable receivers achieves a NF of 3-5dB from 0.2GHz to 3GHz, out-of-band IIP3 of 21.2dBm, and maximum gain of 45dB, respectively. The front-end consumes 13mA current at 0.2GHz and 27.5mA at 3GHz from a 1.2V voltage supply.

This paper presents a CMOS RF tunable 4th-order active bandpass filter with the proposed inductor-less biquads. The NMOS cross-coupled pair is utilized in the biquad for the positive-feedback to form the complex pole, which enables the filter working at high frequency of 5GHz with low power of only 4.8mW from 1.2V power supply. Due to the inductor-less topology, the proposed filter only occupies 0.011mm2silicon area, which is cost-efficient and suitable for integration on chip. The center frequency can be tuned from 2GHz to 5GHz, and the Q factor is tuned from 2 to 8 to cover different bandwidth from 250MHz to 2.5GHz, which makes it suitable for the multi-band/multi-mode and SDR applications. The filer is demonstrated in a standard 65nm CMOS process. As for the center frequency of 5GHz and Q of 2, the simulated P1dB is -6.7dBm, and the simulated input referred noise (IRN) density is 14.2nV/sqrt(Hz).

This paper presents an 8th-order chebyshev active-RC analog baseband IC with tunable cut-off frequency from 500K to 16MHz and adjustable gain from 5.5dB to 70dB for a Software-Defined Radio (SDR) receiver. For the analog baseband, a highly power-efficient push-pull op-amp with two differential-to-single output stages is proposed, which is suitable for the advanced deep-submicron CMOS process. It achieves 45dB gain and 850MHz GBW with only 0.8mA current. I/Q analog baseband IC, consisting of filter, PGA/VGA, and DCOC, is integrated for a SDR receiver, which is fabricated in a standard 65nm CMOS technology. It consumes 9.2mA current from 1.2V power supply, achieves 17.44dBm in-band OIP3, 11.43nV/√Hz input-referred noise (IRN) density, and occupies 0.68mm2silicon area.

In this paper, a low in-band phase noise integer-N CMOS frequency synthesizer is proposed for global navigation satellite system (GNSS) receiver. The synthesizer adopts dual-loop architecture, which consists of a double-balanced mixer and two full PLL loops, to reduce the divide ratio so as to lower the in-band phase noise. It achieves 1MHz resolution and -99 dBc/Hz@10kHz with fixed reference clock of 10MHz, which is compatible to commercial atomic frequency sources. Moreover, a novel adaptive frequency calibration policy is implemented to avoid mis-locking at the unwanted mirror frequency. The PLL is fabricated in 0.18-μm CMOS technology, covers most GPS, Galileo and Beidou-II bands and was integrated in a GNSS receiver with 46MHz intermediate frequency (IF).

This paper presents an ultra-low power 6th-order 7MHz-to-20MHz tunable active-RC low-pass filter. Due to the proposed highly power-efficient Opamp, the filter only consumes 0.47 mA power from 1.8 V supply voltage, corresponding to 3.86 pW/Hz/pole normalized power. The Opamp utilizes an adaptive-biased pole-cancellation push-pull buffer to greatly reduce the power consumption. An adaptive bias circuit is proposed to cooperate with the Opamp to tolerate the PVT variations. The filter achieves 20.9 dBm in-band IIP3, and 298 μVrms integrated input-referred noise. The chip is fabricated in a standard 0.18 μm CMOS process, and occupies 0.21 mm2silicon area without ESD/pads.