A novel technique, CLIP , is presented for the automatic generation of optimal layouts of CMOS cells in the two-dimensional (2D) style. CLIP is based on integer-linear programming ( ILP ) and solves both the width and height minimization problems for 2D cells. Width minimization is formulated in a precise form that combines all factors influencing the 2D cell width—transistor placement, diffusion sharing, and vertical interrow connections—in a common problem space; this space is then searched in a systematic manner by the branch-and-bound algorithms used by ILP solvers. For height minimization, cell height is modeled accurately in terms of the horizontal wire routing density, and a minimum-height layout is found from among all layouts of minimum width. For exact width minimization alone, CLIP 's run times are in seconds for large circuits with 30 or more transistors. For both height and width optimization, CLIP is practical for circuits with up to 20 transistors. To extend CLIP to larger circuits, hierarchical methods are necessary. Since CLIP is optimum under the modeling assumptions, its layouts are significantly better than those generated by other, heuristic, layout tools.

Folding, a key requirement in high-performance cell layout, implies breaking a large transistor into smaller, equal-sized transistors (legs) that are connected in parallel and placed contiguously with diffusion sharing.We present a novel technique FCLZP that integrates folding into the generation of optimal layouts of CMOS cells in the twodimensional (2-D) style.FCLZP is based on integer linear programming (ILP) and precisely formulatm cell width minimization as a O-1 optimization problem.Folding is incorporated into the O-1 ILP model by variables that represent the degrees of freedom that folding introduces into cell layout.FCLZP yields optimal resul@ for three reasons: (1) it implicitly explores all possible transistor placements; (2) it considers all diffusion sharing possibilities among folded transistors; and (3) when paired P and N transistors have unequal numbers of legs, it considers all their relative positions.FCLZP is shown to be practical for relatively large circuits with up to 30 transistors.We then extend FCLZP to accommodate and-stack clustering, a requirement in most practical designs due to its benefiti on circuit performance.This reduces run times dramatically, making FCLZP viable for much larger circuits.It also demonstrates the versatility of FCLZP'S ILP-based approach in easily accommodating additional design constraints. INTRODUCTIONCell layout synthesis falls in the category of constrained optimization \vhose goal is to find a solution that optimizes some cost function under a set of constraints.The cost function can be the cell area, its delay, or a combination of these.The constraints include bounds on \vidth or height, aspect ratio, number of diffusion rolvs, or the maximum size of transistors.Since cell layout optimization is NP-hard [3], any exact algorithm can, in the }vorst case, have an Ped

We present a novel technique CLIP for optimizing both theheight and width of CMOS cell layouts in the two-dimensional (2-D) style. CLIP is based on integer-linear programming (ILP) and proceeds in two stages: First, an ILP model is used to determine a 2-D layout of minimum width W cell . Then, another model generatesa 2-D layout that has width W cell and requires a minimumnumber of routing tracks. Run times are in seconds for circuitswith up to 16 transistors. For larger circuits, we extend CLIP to ahierarchical method HCLIP that places series-connected transistorscontiguously. This reduces run times by up to three orders ofmagnitude, and still yields optimal results in over 80% of cases.

We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Runtimes for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality.