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Franz Fink

dblp:07/1883 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 1992
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
3 papers
Electronic design automation · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › delay fault testing
path delay fault
0.021992
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns · IEEE Trans. Computers 1992
DYNAMITE: an efficient automatic test pattern generation system for path delay faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › hardware verification and test
fault simulation
0.021992
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns · IEEE Trans. Computers 1992
Parallel Pattern Fault Simulation of Path Delay Faults · DAC 1989
Electronic design automation
hardware verification and test
0.021992
Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns · IEEE Trans. Computers 1992
Parallel Pattern Fault Simulation of Path Delay Faults · DAC 1989
Electronic design automation › hardware verification and test
delay fault testing
0.011991
DYNAMITE: an efficient automatic test pattern generation system for path delay faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation
hardware test
0.011991
DYNAMITE: an efficient automatic test pattern generation system for path delay faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › hardware verification and test
test generation
0.011991
DYNAMITE: an efficient automatic test pattern generation system for path delay faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991
Electronic design automation › hardware verification and test › fault simulation
path delay fault simulation
0.011989
Parallel Pattern Fault Simulation of Path Delay Faults · DAC 1989
Electronic design automation › hardware verification and test › test generation
path sensitization
0.011991
DYNAMITE: an efficient automatic test pattern generation system for path delay faults · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1991

Methods — techniques the papers use, named apart from their topics

parallel processing · 0.0three-valued logic · 0.0ten-valued logic · 0.0path selection · 0.0implication procedure · 0.0parallel pattern processing · 0.0
YearPublicationVenuePosition
1992 Robust and Nonrobust Path Delay Fault Simulation by Parallel Processing of Patterns
abstract
An accelerated fault simulation approach for path delay faults is presented. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and nonrobust decision of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.>
Franz Fink, Karl Fuchs, Michael H. Schulz
IEEE Trans. Computers1
1991 DYNAMITE: an efficient automatic test pattern generation system for path delay faults
abstract
The authors present DYNAMITE, a versatile and efficient automatic test pattern generation system for path delay fault. Based upon a ten-valued and a three-valued logic, the deterministic test pattern generation algorithm incorporated in DYNAMITE is capable of generating both robust and nonrobust tests for path delay faults. Particular emphasis has been placed on coping with the main disadvantage of the path delay fault model. The distinct features of DYNAMITE consist of the application of a powerful implication procedure and a stepwise path sensitization procedure, which has the capability of proving large numbers of path faults as redundant by a single test generation attempt. The delay test generation process is further optimized by the use of a new path selection procedure which aims at the identification of paths, which can successfully be sensitized, and the elimination of redundant, i.e., unsensitizable, paths.>
Karl Fuchs, Franz Fink, Michael H. Schulz
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
1989 Parallel Pattern Fault Simulation of Path Delay Faults
abstract
This paper presents an accelerated fault simulation approach for path delay faults. The distinct features of the proposed fault simulation method consist in the application of parallel processing of patterns at all stages of the calculation procedure, its versatility to account for both robust and non-robust detection of path delay faults, and its capability of efficiently maintaining large numbers of path faults to be simulated.
Michael H. Schulz, Franz Fink, Karl Fuchs
DAC2