Demo Data from VLDB 2026 / reviewers in the wild / expert
Etienne Lantreibecq
dblp:07/2035
· DBLP profile ↗
4ranked-venue papers
2as first author
0since 2021 · last 2014
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Software engineering, systems software and programming languages · 3 · 2 first-authorSystems, architecture and hardware · 1Theory of computation · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 32% Performance modeling and evaluation · 32% Integrated circuit design · 30% |
Topics — the 8 heaviest of 8, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › asynchronous circuit design
globally asynchronous locally synchronous design |
0.1 | 1 | 2009 | Towards Performance Prediction of Compositional Models in Industrial GALS Designs · CAV 2009 |
Electronic design automation › hardware verification and test
hardware verification |
0.1 | 1 | 2009 | Towards Performance Prediction of Compositional Models in Industrial GALS Designs · CAV 2009 |
Performance modeling and evaluation
performance prediction |
0.1 | 1 | 2009 | Towards Performance Prediction of Compositional Models in Industrial GALS Designs · CAV 2009 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 2009 | Towards Performance Prediction of Compositional Models in Industrial GALS Designs · CAV 2009 |
Processor architecture and microarchitecture
chip multiprocessor |
0.0 | 1 | 1999 | Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design · DAC 1999 |
Integrated circuit design
system-on-chip |
0.0 | 1 | 1999 | Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design · DAC 1999 |
Electronic design automation › system-level design › system design methodology
system-on-chip design flow |
0.0 | 1 | 1999 | Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design · DAC 1999 |
Electronic design automation
hardware/software co-design |
0.0 | 1 | 1999 | Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design · DAC 1999 |
Methods — techniques the papers use, named apart from their topics
virtual component reuse · 0.0emulation · 0.0c modeling · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2014 | Formal analysis of a hardware dynamic task dispatcher with CADP
Etienne Lantreibecq, Wendelin Serwe |
Sci. Comput. Program. | 1 |
| 2011 | Model Checking and Co-simulation of a Dynamic Task Dispatcher Circuit Using CADP
Etienne Lantreibecq, Wendelin Serwe |
FMICS | 1 |
| 2009 | Towards Performance Prediction of Compositional Models in Industrial GALS Designs
Nicolas Coste, Holger Hermanns, Etienne Lantreibecq, Wendelin Serwe |
CAV | 3 |
| 1999 | Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor DesignabstractThis paper describes a new design flow that significantly reduces time-to-market for highly complex multiprocessor-based System-On-Chip designs.This flow, called Fast Prototyping, enables concurrent hardware and software development, early verification and productive re-use of intellectual property.We describe how using this innovative system design flow, that combines different technologies, such as C modeling, emulation, hard Virtual Component re-use and CoWare N2C™, we achieve better productivity on a multi-processor SOC design.1.1 Benoit Clement, Richard Hersemeule, Etienne Lantreibecq, Bernard Ramanadin, Pierre Coulomb, François Pogodalla |
DAC | 3 |