In low-power wide-area network (LPWAN) protocols (such as LoRaWAN), orthogonalq-ary modulation is often employed because of its high capacity. It is well established thatq-ary coded modulation (CM) operates close to the Shannon limit at very low SNR. In this scheme, symbols from a non-binary (NB) error correction code defined over GF(q) are directly mapped to a set ofqorthogonal modulation symbols. However, the high decoding complexity for large alphabet sizes (q∈ [64 1024]) has so far prevented practical adoption. This study presents the first high-throughput software decoder for non-binary polar (Non-Binary polar (NB-p)) codes. We introduce the Dual-Probability-Frequency Fast Successive Cancellation (DPF-FSC) decoding algorithm, which operates jointly in probability and frequency domains to reduce the computational complexity. Combined with graph pruning techniques and optimized for parallel execution on multicore SIMD architectures, our implementation achieves real-time performance suitable for software-defined radio (SDR) and cloud-RAN systems. In particular, we demonstrate that our proposed DPF-FSC decoder achieves throughputs ranging from several Mbps on low-power embedded processors to over 500 Mbps on modern multicore CPUs. The most optimized implementation (D2b) reaches up to 900 Mbps on high-end processors for codes over GF(16) with 256 symbols and a 20% coding rate in single-core configuration. The throughput is reduced for larger Galois fields (GF(64) and GF(256)), but can still reach throughputs 40 to 400 Mbps, respectively, depending on the coding rate.

As successfully adopted in standard long code scenarios, belief propagation (BP) decoding has been considered a promising universal decoding candidate for next-generation wireless communications. However, when applied to short codes, BP decoding suffers from poor error correction performance due to harmful cycle structures in the Tanner graph. In this paper, we address this issue by designing a structured, sparse parity-check matrix (ssPCM) framework, composed of multiple cycle-free parity-check row blocks (PCRBs). The resulting ssPCMs feature regular row weights and perform better than the state-of-theart 4 -cycle-free row redundant PCMs across Bose-Chaudhuri-Hocquenghem (BCH) codes of length 63.

Belief propagation (BP) decoding has been recognized for its capacity-approaching performance and high throughput when decoding long low-density parity-check (LDPC) codes. However, the application of BP decoding for short codes is hindered by dense parity-check matrices (PCMs) and prevalent short cycles in the Tanner graph. In this paper, we introduce a general method to extract an optimized sparse PCM for short binary block codes, which removes length-four cycles and enhances the connectivity of short cycles to enable BP decoding with improved performance. Notably, for short binary codes with lengths up to 64, our BP decoding performance approaches the maximum likelihood bound and surpasses the best-reported BP results with reduced computational complexity. Compared with other universal decoding algorithms, BP decoding using our extracted sparse PCMs is competitive in terms of both error-rate performance and computational complexity. These promising results suggest that our method to improve BP decoding for short codes is a step toward a practical universal BP decoder for next-generation communication systems.

Next-generation channel coding has stringent demands on throughput, energy consumption, and error rate performance while maintaining key features of 5G New Radio (NR) standard codes such as rate compatibility, which is a significant challenge. Due to excellent capacity-achieving performance, spatially-coupled low-density parity-check (SC-LDPC) codes are considered a promising candidate for next-generation channel coding. In this paper, we propose an SC-LDPC code family called edge-spreading Raptor-like (ESRL) codes. Unlike other SC-LDPC codes that adopt the structure of existing rate-compatible LDPC block codes before coupling, ESRL codes maximize the possible locations of edge placement and focus on constructing an optimal coupled matrix. Moreover, a new graph representation called the unified graph is introduced. This graph offers a global perspective on ESRL codes and identifies the optimal edge reallocation to optimize the spreading strategy. We conduct comprehensive comparisons of ESRL codes and 5G-NR LDPC codes. Simulation results demonstrate that when all decoding parameters and complexity are the same, ESRL codes have obvious advantages in error rate performance and throughput compared to 5G-NR LDPC codes in some specific scenarios (low and high number of iterations), making them a promising solution towards next-generation channel coding.

This paper introduces a novel type of sequences called C4-sequences. C4-sequences share similar optimal autocorrelation properties with Zadoff-Chu sequences. However, C4-sequences offer the additional advantage of being also optimal (in the sense of minimal Euclidean distance between sequences) for four truncation lengths, providing flexibility in adapting to different channel conditions without compromising performance. Moreover, unlike Zadoff-Chu sequences, the points of a constellation associated with a C4-sequence are not limited to the unit circle. This opens up possibilities for achieving shaping gain, leading to enhanced spectral efficiency. By combining a truncated C4-sequence modulation as an inner code with a fixed-rate non-binary outer code, flexible and performant rate-adaptive communication systems can also be achieved. Finally, the notion of C4-sequences can be generalized.

For very high-speed satellite communication (up to 10 Gbit/s), the natural level of parallelism of a single decoder might be insufficient to achieve the decoding throughput. A known solution is to implement several decoder cores working in parallel. This solution entails efficient control and design of the input and output buffers to regulate the varying number of decoding iterations of each decoder. This paper presents a methodology to build such a system effectively for iterative decoders with stopping criteria. As an application, we present the result of the implementation of 3 DVB-S2/S2X decoders in a single FPGA. Simulation results of the whole system show performance within (or very close to) the standard requirements. The implementation can handle code rates from 13/45 (3.3 Gbit/s air throughput) up to 9/10 (10 Gbit/s air throughput) for several modulation sizes.

Non-Binary LDPC codes are known to have good decoding capability and high decoding complexity. Therefore, their utilization is limited to low-rate applications such as BeiDou, the Chinese Global Navigation Satellite Systems. Recently, a new decoding algorithm called the Best, Requested, and Default algorithm has been proposed. The algorithm significantly reduces the size of exchanged messages between the variable nodes and check nodes leading to simplifying the hardware architecture. This paper presents the adaptation and the impact of the algorithm on the Extended Min-Sum Forward-Backward check node processor. The proposed decoder is simulated for several code rates and negligible degradation is observed compared to the classical EMS algorithm. In addition, the proposed decoder is synthesized on FPGA in a fully-parallel fashion. The proposed decoder requires only 42% of the memory allocations and 85% of the computational resources of the classical EMS decoder.

A new efficient preamble-less short frame, called Quasi-Cyclic Short Packet (QCSP), has been recently proposed for the Internet of Things (IoT) deployment. It has demonstrated its good performances in the process of detection, synchronization, and error correction in an asynchronous Additive White Gaussian Noise (AWGN) channel, with residual frequency offset, and at a very low Signal-to-Noise Ratio (SNR). The detection process uses the normalized score of a non-coherent frame match filter to assess the presence of a frame or not. In this paper, we improve the detection performance by combining non-coherent detection with coherent detection. The proposed method decreases the probability of miss-detection by two decades, for a given probability of false alarm.

This paper proposes a phase and frequency synchronization technique in the context of Cyclic Code Shift Keying (CCSK) modulation associated with Non-Binary Low Density Parity Check Matrix (NB-LDPC) codes. Two methods are proposed. The first, called Direct Method (DM), is a direct estimation of the parameters of a noisy sinusoidal. The second, called Parametric Method (PM), is based on the Maximum Likelihood estimation using a distribution parameterized by the CCSK demodulator and the NB-LDPC decoder. The Frame Error Correction (FEC) results show that the performance of the proposed phase synchronized frame approximately maintains the same performance as when a Genius-Aided estimation is used, or when no phase offset exists. This is achieved at a very low Signal to Noise Ratio (SNR) around -10 dB.

In the above article[1], the definition of polynomials$P_{9}[X]$an$P_{10}[X]$in (1) was incorrect.$P_{9}[X]=1+X^{5}+X^{9}$should b replaced by$P_{9}[X]=1+X^{4}+X^{9}$and$P_{10}[X]=1+X^{4}+X^{1}$should be replaced by$P_{10}[X]=1+X^{3}+X^{10}$.

This paper proposes a new method of constructing compact fully-connected Quasi-Cyclic Low Density Parity Check (QC-LDPC) codes with girth$g$= 8, 10, and 12. The originality of the proposed method is to impose constraints on the exponent matrix P to reduce the search space drastically. For a targeted lifting degree of$N$, the first step of the method is to sieve the integer ring$\mathbb {Z}_{N}$to make a particular sub-group with specific properties to construct the second column of P (the first column being filled with zeros). The remaining columns of P are determined recursively as multiples of the second column by adapting the sequentially multiplied column (SMC) method whereby a controlled greedy search is applied at each step. The codes constructed with the proposed semi-algebraic method show lengths that can be significantly shorter than their best counterparts in the literature.

In this paper, we present a frame structure that can be viewed as a preamble for the detection and synchronization process (leading to low cost receiver) and as an encoded codeword carrying the transmitted message (leading to reliable transmission). This duality facilitates an ALOHA protocol avoiding preamble overhead. The frame structure, named Quasi-Cyclic Short Packet (QCSP), is based on the association of a Cyclic Code Shift Keying (CCSK) modulation and a non-binary error control code. The detection/correction algorithm of the QCSP system is presented, its performance is theoretically derived and discussed for different parameters. A QCSP frame can be transmitted and received correctly with an error probability of$\mathbf {10^{-4}}$, distanced by1.2dB from Polyanskiy’s bound (an estimated Shannon’s limit for small packet size) at −11 dB of SNR for a payload of 360 bits. Compared to a classical preamble-based frame using a modern binary error control code, the size of a QCSP frame is reduced by 23%. Moreover, detecting a QCSP frame requires a lower complexity than detecting a longer classical preamble.

Efficient short Packet transmission is a key technique of the Internet of Things systems. When the data payload is small, the header used to help the receiver synchronization process becomes no longer negligible and should be shortened, and ideally removed. A Preamble-less frame generated using a non-binary error control code associated with a Cyclic Code Shift Keying (CCSK) modulation has been recently proposed. The paper presents a pragmatic approach to mitigate the time synchronization ambiguity at two levels: at symbol level thanks to an over-modulation of the CCSK symbols, and at chip level thanks to the Non-Binary code properties. Simulation results showed the efficiency of the proposed approach, where the blind frame synchronization is successfully performed at -10 dB.

This paper proposes a new finite precision iterative decoder for low-density parity-check (LDPC) codes. The proposed decoder, named Sign-Preserving Min-Sum (SP-MS), significantly improves the decoding performance compared to the classical Offset Min-Sum (OMS) decoder when messages are quantized on$q=2$, 3, or 4 bits. The particularity of the SP-MS decoder is that messages cannot take the 0 value, and can fully benefit from the$q$bits of precision. The optimization of the SP-MS decoder is investigated in the asymptotic limit of the code length using density evolution (DE). Our study shows that 3-bit SP-MS decoders can achieve the same error-correcting performance as 5-bit OMS decoders, and 2-bit SP-MS decoders outperform 3-bit OMS decoders. The finite-length simulations confirm the conclusions of the DE analysis for several LDPC codes. Our SP-MS decoder shows a signal-to-noise ratio (SNR) gain up to 0.43 dB, with a memory/wire reduction of up to 40%, compared to the OMS decoder. Moreover, the SP-MS decoder converges faster and uses fewer iterations than the OMS decoder, with an improvement of up to 83.3% of the average decoding throughput. On an FPGA, the SP-MS decoder reduces resource utilization by up to 56% compared to the OMS decoder.

Decoding using the dual trellis is considered as a potential technique to increase the throughput of soft-input soft-output decoders for high coding rate convolutional codes. However, the dual Log-MAP algorithm suffers from a high decoding complexity. More specifically, the source of complexity comes from the soft-output unit, which has to handle a high number of extrinsic values in parallel. In this paper, we present a new low-complexity sub-optimal decoding algorithm using the dual trellis, namely the dual Max-Log-MAP algorithm, suited for high coding rate convolutional codes. A complexity analysis and simulation results are provided to compare the dual Max-Log-MAP and the dual Log-MAP algorithms. Despite a minor loss of about 0.2 dB in performance, the dual Max-Log-MAP algorithm significantly reduces the decoder complexity and makes it a first-choice algorithm for high-throughput high-rate decoding of convolutional and turbo codes.

This paper proposes a new soft-input soft-output decoding algorithm particularly suited for low-complexity high-radix turbo decoding, called local soft-output Viterbi algorithm (local SOVA). The local SOVA uses the forward and backward state metric recursions just as the conventional Max-Log-MAP algorithm does, and produces soft outputs using the SOVA update rules. The proposed local SOVA exhibits a lower computational complexity than the Max-Log-MAP algorithm when employed for high-radix decoding in order to increase throughput, while having the same error correction performance even when used in a turbo decoding process. Furthermore, with some simplifications, it offers various trade-offs between error correction performance and computational complexity. For instance, employing the local SOVA algorithm for radix-8 decoding of the LTE turbo code reduces the complexity by 33% without any performance degradation and by 36% with a slight penalty of only 0.05 dB. Moreover, the local SOVA algorithm opens the door for the practical implementation of turbo decoders for radix 16 and higher.

The construction of a quasi-cyclic low density parity-check (QC-LDPC) matrix is usually carried out in two steps. In the first step, a prototype matrix is defined according to certain criteria (size, girth, check and variable node degrees, and so on). The second step involves the expansion of the prototype matrix. During this last phase, an integer value is assigned to each non-null position in the prototype matrix corresponding to the right-rotation of the identity matrix. The problem of determining these integer values is complex. The state-of-the-art solutions use either some mathematical constructions to guarantee a given girth of the final QC-LDPC code, or a random search of values until the target girth is satisfied. In this paper, we propose an alternative/complementary method that reduces the search space by defining large equivalence classes of topologically identical matrices through row and column permutations using additive, structural, and multiplicative transformations. Selecting only a single element per equivalence class can reduce the search space by a few orders of magnitude. Then, we use the formalism of constraint programming to list the exhaustive sets of solutions for a given girth and a given expansion factor. An example is presented in all sections of the paper to illustrate the methodology.

This paper generalizes the method proposed by Poulliat et al. for the determination of the optimal Galois field coefficients of a non-binary LDPC parity check constraint based on the binary image of the code. Optimal, or almost-optimal, parity check coefficients are given for check degree varying from 4 to 20 and Galois field varying from GF (64) up to GF (1024). For all given sets of coefficients, no codeword of Hamming weight two exists. A reduced complexity algorithm to compute the binary Hamming weight 3 of a parity check is proposed. When the number of sets of coefficients is too high for an exhaustive search and evaluation, a local greedy search is performed. Explicit tables of coefficients are given. The proposed sets of coefficients can effectively replace the random selection of coefficients often used in NB-LDPC construction.

In this paper, we define Noise-against-Noise Min-Sum (NAN-MS) decoders as decoders that incorporate a certain amount of random perturbation due to deliberate noise injection. We introduce a noise model which is used to implement quantized NAN-MS decoders, using a limited number of precision bits. The behavior of NAN-MS decoders is investigated in the asymptotic limit of the code length using a noisy version of density evolution (DE). We use the noisy-DE thresholds to analyze and optimize the noise model parameters. We show that a controlled injection of noise allows NAN-MS decoders to achieve better performance than noiseless MS decoders, especially for low precision. The finite-length simulations confirm the conclusions of the DE analysis.

Non-binary low-density parity-check codes have superior communications performance compared to their binary counterparts. However, to be an option for future standards, efficient hardware architectures must be developed. State-of-the-art decoding algorithms lead to architectures suffering from low throughput and high latency. The check node function accounts for the largest part of the decoders overall complexity. In this paper a new hardware aware check node algorithm and its architecture is proposed. It has state-of-the-art communications performance while reducing the decoding complexity. The presented architecture has a 14 times higher area efficiency, increases the energy efficiency by factor 2.5 and reduces the latency by factor of 3.5 compared to state-of-the-art architectures.

A modified Gradient Descent Bit Flipping (GDBF) algorithm is proposed for decoding Low Density Parity Check (LDPC) codes on the binary-input additive white Gaussian noise channel. The new algorithm, called Noisy GDBF (NGDBF), introduces a random perturbation into each symbol metric at each iteration. The noise perturbation allows the algorithm to escape from undesirable local maxima, resulting in improved performance. A combination of heuristic improvements to the algorithm are proposed and evaluated. When the proposed heuristics are applied, NGDBF performs better than any previously reported GDBF variant, and comes within 0.5 dB of the belief propagation algorithm for several tested codes. Unlike other previous GDBF algorithms that provide an escape from local maxima, the proposed algorithm uses only local, fully parallelizable operations and does not require computing a global objective function or a sort over symbol metrics, making it highly efficient in comparison. The proposed NGDBF algorithm requires channel state information which must be obtained from a signal to noise ratio (SNR) estimator. Architectural details are presented for implementing the NGDBF algorithm. Complexity analysis and optimizations are also discussed.

This work extends the analysis and application of a digital error correction method called Muller C-element Decoding (MCD), which has been proposed for fault masking in logic circuits comprised of unreliable elements. The proposed technique employs cascaded Muller C-elements and XOR gates to achieve efficient error-correction in the presence of internal upsets. The error-correction analysis of MCD architecture and the investigation of C-element's robustness are first introduced. We demonstrate that the MCD is able to produce error-correction benefit in a high error-rate of internal faults. Significantly, for a (3,6) short-length Low Density Parity Check (LDPC) code, when the decoding process is internally error-free the MCD achieves also a gain in terms of decoding performance by comparison to the well-known Gallager Bit-Flipping method. We further consider application of MCD to a general-purpose fault-tolerant model, coded Dual Modular Redundancy (cDMR), which offers low-redundancy error-resilience for contemporary logic systems as well as future nanoeletronic architectures.

In this paper, we investigate the performance of Single-Carrier (SC) transmission with Non-Binary Low-Density Parity-Check (NB-LDPC) coded Cyclic Code-Shift Keying (CCSK) signaling in a multipath environment and we show that the combination of CCSK signaling and non-binary codes results in two key advantages, namely, improved Log-Likelihood Ratio (LLR) generation via correlations and reduced implementation complexity. We demonstrate that Maximum Likelihood (ML) demodulation can be expressed by two circular convolution operations and thus it can be processed in the frequency domain. Then, we propose a joint Frequency-Domain Equalization (FDE) and LLR generation scheme that aims at reducing the complexity of the receiver. Finally, we demonstrate through Monte-Carlo simulations and histogram analysis that this proposed CCSK signaling scheme gives more robustness to SC-FDE systems than commonly employed Hadamard signaling schemes (a gap of ≈ 1.5dB in favor of CCSK signaling is observed at BER = 10-5, assuming perfect Channel State Information).

Classically, the association of high-order modulation techniques to binary channel coding suffers from significant information loss due to the computation of the channel probabilities at the bit level. In this paper, we investigate the association of Non-Binary Low-Density Parity-Check codes (NB-LDPC) and Cyclic Code-Shift Keying (CCSK) which aims at preventing the information loss by computing the probabilities at the symbol level. Simulation results over Gaussian and Rayleigh channels demonstrate that this association leads to significant performance gains (≈ 2.6dB over the Gaussian channel and ≈ 3.5dB over the Rayleigh channel).

A decoding algorithm and logic implementation is proposed for fast, low-complexity error correction in environments with a high rate of transient faults as well as hard errors. The circuit is able to correct a single error in one clock cycle, making it suitable for mitigating faults in pipelined digital logic systems. The proposed method is also resilient against internal transient gate errors that may occur within the decoder itself. In the presence of a high input error rate (0.001) and high internal gate fault rate (10-5), the new decoding algorithm is able to reduce the error probability by two orders of magnitude. An asynchronous implementation is also presented for the new algorithm, which performs iterative error-correction with reduced latency compared to synchronous algorithms.

This paper presents a bottom up approach for implementing high throughput, scalable, layered LDPC decoding architecture for multi-standard applications. A generic implementation of fully parallel check node along with a block level Channel Memory organization scheme are two elements of novelty of this work. The proposed decoder IP core is synthesizable for all codes defined by WiMAX (WiFi) standards. Synthesis results are presented based on 130 nm standard cell ASIC technology.

This paper describes an efficient graph-based method to optimize data-flow expressions for best hardware implementation. The method is based on factorization, common subexpression elimination (CSE) and decomposition of algebraic expressions performed on a canonical representation, Taylor Expansion Diagram. The method is generic, applicable to arbitrary algebraic expressions and does not require specific knowledge of the application domain. Experimental results show that the DFGs generated from such optimized expressions are better suited for high level synthesis, and the final, scheduled implementations are characterized, on average, by 15.5% lower latency and 7.6% better area than those obtained using traditional CSE and algebraic decomposition.

Layered decoding is known to provide efficient and high-throughput implementation of LDPC decoders. However, the implementation of the layered architecture is not always straightforward because of the memory access conflicts in the a-posteriori information memory. In this paper, we focus our attention on a particular type of conflict introduced by the existence of multiple diagonal matrices in the DVB-T2 parity check matrix structure. We illustrate how the reordering of the matrix reduces the number of conflicts, at the cost of limiting the level of parallelism. We then propose a parity extending process to solve the remaining conflicts. Fixed point simulation results show coherent performance without modifying the layered architecture.

Interconnects are now considered as the bottleneck in the design of system-on-chip (SoC) since they introduce delay and power consumption. To deal with this issue, data-coding for interconnect power and timing optimization is a promising method. Based on some realistic observations on interconnect delay and power estimation, a new data-coding technique called ldquoConvolutional Encoder for Crosstalk Reductionrdquo (CECR) is proposed. It allows the reduction of delay, power consumption (including extra power consumption due to codecs) and noise for on-chip buses. The concept of the technique is to reduce the switching activity to its minimum considering the transmission of data on the encoded wires. Results show the technique efficiency for different technologies and bus lengths. The power consumption reduction can reach up to 12% for a 10 mm bus in the 65 nm technology and more if buses are longer. It also allows the acceleration of the data propagation of 20% and the reduction of the overall worst noise case transitions of 51%.

Non-binary LDPC codes are now recognized as a potential competitor to binary coded solutions, especially when the codeword length is small or moderate. More and more works are reported with good performance/complexity tradeoffs, which make non-binary solutions interesting for practical applications, such as 4G-wireless systems or DVB-like systems. In this paper, we show that proposing non-binary LDPC codes built on finite fields is actually a limitation, both from performance and implementation points of view. By considering non-binary codes on the general linear group, we show in particular that a slight performance improvement can be obtained, compared to Galois Field codes, with reasonable additional cost in the hardware implementation. The performance gain is quite small, but comes at a slight extra decoding cost, and is obtained by proper generalization of the code optimization techniques that are standard for non-binary LDPC codes on fields.

An efficient graph-based method to optimize polynomial expressions in data-flow computations is presented. The method is based on the factorization, common-subexpression elimination, and decomposition of algebraic expressions performed on a canonical Taylor expansion diagram representation. It targets the minimization of the latency and hardware cost of arithmetic operators in the scheduled implementation. The generated data-flow graphs are better suited for high-level synthesis than those extracted directly from the initial specification or obtained with traditional algebraic decomposition methods. Experimental results show that the resulting implementations are characterized by better performance and smaller datapath area than those obtained using traditional algebraic decomposition techniques. The described method is generic, applicable to arbitrary algebraic expressions, and does not require any knowledge of the application domain.

This letter proposes a quasi optimum maximum likelihood detection technique based on Geometrical Diversification and Greedy Intensification (GDGI). The presented detector scheme is shown to achieve almost optimal performance for all signal-to-noise ratio (SNR) values and a cubic computation complexity in the problem dimension. It possesses a regular structure well suited for hardware implementation. Simulation results show that for a system with a high dimension of n = 60, the loss is approximately 0.35 dB at BER=10-5compared to an optimal decoding.

An original technique to transform functional representation of the design into a structural representation in form of a data flow graph (DFG) is described. A canonical, word-level data structure, Taylor expansion diagram (TED), is used as a vehicle to effect this transformation. The problem is formulated as that of applying a sequence of decomposition cuts to a TED that transforms it into a DFG optimized for a particular objective. A systematic approach to arrive at such a decomposition is described. Experimental results show that such constructed DFG provides a better starting point for architectural synthesis than those extracted directly from HDL specifications

This tutorial paper gives an overview of the implementation aspects related to turbo decoders, where the term turbo generally refers to iterative decoders intended for parallel concatenated convolutional codes as well as for serial concatenated convolutional codes. We start by considering the general structure of iterative decoders and the main features of the soft-input soft-output algorithm that forms the heart of iterative decoders. Then, we show that very efficient parallel architectures are available for all types of turbo decoders allowing high-speed implementations. Other implementation aspects like quantization issues and stopping rules used in conjunction with buffering for increasing throughput are considered. Finally, we perform an evaluation of the complexities of the turbo decoders as a function of the main parameters of the code.

Through a rapid survey of the architecture of low-density parity-check (LDPC) decoders, this paper proposes a general framework to describe and compare the LDPC decoder architectures. A set of parameters makes it possible to classify the scheduling of iterative decoders, memory organization, and type of check-node processors and variable-node processors. Using the proposed framework, an efficient generic architecture for nonflooding schedules is also given.

This paper describes an efficient method to perform factorization of DSP transforms based on Taylor expansion diagram (TED). It is shown that TED can efficiently represent and manipulate mathematical expressions. We demonstrate that it enables efficient factorization of arithmetic expressions of DSP transforms, resulting in a simplification of the computation

In this paper we present our contribution in terms of synchronization processor for a SoC design methodology based on the theory of the latency insensitive systems (LIS) of Carloni et al. (2001). Our contribution consists in IP encapsulation into a new wrapper model whose speed and area are optimized and synthetizability guaranteed. The main benefit of our approach is to preserve the local IP performance when encapsulating them and reduce SoC silicon area.

This paper presents our contribution in terms of synchronization processor to a SoC design methodology based on the theory of the latency insensitive systems (US). This methodology 1) promotes pre-developed IPs intensive reuse, 2) segments inter-IPs interconnects with relay stations to break critical paths and 3) brings robustness to data stream irregularities to IPs by encapsulation into a synchronization wrapper. Our contribution consists of IP encapsulation into a new wrapper model containing a synchronization processor, which speed and area are optimized and synthesizability guaranteed. The main benefit of our approach is to preserve the local IP performances when encapsulating them. This approach is part of the RNRT ALIPTA project which targets design automation of intensive digital signal processing systems with GAUT, a high-level synthesis tool.

An efficient sub-optimal algorithm, called HIS (hyperplane intersection and selection) detection algorithm, is proposed to solve the problem of joint detection of K users in an MC-CDMA system. Compared to existing solutions, the proposed algorithm has three characteristics very attractive for practical. systems. Firstly, it has nearly optimal performance. Secondly, it has a low computational complexity - O(K/sup 2/) multiplications and O(K/sup 3/) additions. Third, the algorithm has an inherent parallelism. To our knowledge, the HIS algorithm is not just an add-on to an existing algorithm, but rather a new decoding technique based on a singular value decomposition of the channel matrix, H. After giving the equation of the MC-CDMA multi-user detection problem, the HIS algorithm is described. Its performance is compared to known existing algorithms (ZF, MMSE, PIC and sphere decoding). For a BER as low as 10/sup -4/, the HIS algorithm introduces only 0.2 dB degradation compared to the optimal sphere decoding algorithm for K=16 users against 3.8 dB for the PIC algorithm with two MMSE stages.

This letter presents the mathematical framework involved in the determination of an upper bound of the maximum spread value of a D-dimensional turbo code of frame size N. This bound is named the sphere bound (SB). It is obtained using some simple properties of Euclidian space (sphere packing in a finite volume). The SB obtained for dimension 2 is equal to /spl radic/2N. This result has already been conjectured. For dimension 3, we prove that the SB cannot be reached, but can be closely approached (at least up to 95%). For dimensions 4-6, the construction of particular interleavers shows that the SB can be approached up to 80%. Moreover, from the SB calculation, an estimate of the minimum Hamming weight of the weight-two input sequence is derived.

The re-use of complex digital signal processing (DSP) coprocessors can be improved using IP cores described at a high abstraction level. System integration, which is a major step in SoC design, requires taking into account communication and timing constraints to design and integrate IP. In this paper, we describe an IP design approach that relies on three main phases: constraints modeling, IP constraints analysis steps for feasibility checking, and synthesis. Based on a generic architecture, the presented method provides automatic generation of IP cores designed under integration constraints. We show the effectiveness of our approach in a case study of a maximum a posteriori (MAP) algorithm for a turbo decoder.

This paper presents several techniques for the very large-scale integration (VLSI) implementation of the maximum a posteriori (MAP) algorithm. In general, knowledge about the implementation of the Viterbi (1967) algorithm can be applied to the MAP algorithm. Bounds are derived for the dynamic range of the state metrics which enable the designer to optimize the word length. The computational kernel of the algorithm is the add-MAX* operation, which is the add-compare-select operation of the Viterbi algorithm with an added offset. We show that the critical path of the algorithm can be reduced if the add-MAX* operation is reordered into an offset-add-compare-select operation by adjusting the location of registers. A general scheduling for the MAP algorithm is presented which gives the tradeoffs between computational complexity, latency, and memory size. Some of these architectures eliminate the need for RAM blocks with unusual form factors or can replace the RAM with registers. These architectures are suited to VLSI implementation of turbo decoders.

The purpose of this paper is to calculate the bit error rate (BER) of a multiband non-coherent on-off keying (OOK) demodulation. The results fit perfectly the simulations of the system. It allows us to study the influence of the filter and the decimation factor on the modulation performance. It is also possible to optimize the system by means of other criteria (e.g. system complexity, jammer sensitivity), thus avoiding time consuming simulations.

A new architecture for survivor memory management in the M algorithm is presented. So far, classical implementations of the survivor memory management employ the register exchange procedure. The architecture presented here is based on the trace back procedure used in the Viterbi algorithm. Using a new pointer which indicates the number of the surviving path given by the sorting operation during the path metric updating operation, all the trace back techniques that have been proposed for the Viterbi algorithm can be employed for the M algorithm. This architecture is specially attractive for large values of M and L in which case the register exchange approach is impractical due to power consumption and to the area required for wiring. In addition, a combination of the register exchange and the trace back procedures is also presented. The combination of these algorithms reduces both the information to be stored and the processing time.

A VLSI structure for path metric updating in the M algorithm is presented. The architecture is based on the combination of a modified Batcher's (1968) odd-even merging network and a bitonic selection procedure. A feature of the trellis structure allows to replace an existing solution based on two 2M-item sorting operations by three M-item sorting operations with an additional one-layer bitonic merge. These three sorting networks and the bitonic merging procedure permit a reduction of up to 50% in hardware complexity.

An architectural study of a Joint Source-Channel Trellis Coding (JSCTC) technique is presented. The use of a sub-optimal trellis search algorithm, the M algorithm, is proposed to encode the source in order to keep the encoding complexity independent of the trellis constraint length (i.e. the codebook size). The idea is to increase the codebook size (and thus, the quality of the transmission) without increasing the hardware complexity. A comparison in terms of complexity versus performance between the M algorithm and the optimal search algorithm (Viterbi) is presented for the encoding of a first-order Gauss-Markov source. In addition, the JSCTC system is compared with a conventional communication system consisting of a JPEG codec and a turbo-codec.

A unified framework is presented in order to build lattice constellations matched to both the Rayleigh fading channel and the Gaussian channel. The method encompasses the situations where the interleaving is done on the real components or on two-dimensional signals. In the latter case, a simple construction of lattices congruent to the densest binary lattices with respect to the Euclidean distance is proposed. It generalizes, in a sense to be clarified later, the structural construction proposed by Forney (1991). These constellations are next combined with coset codes. The partitioning rules and the gain formula are similar to those used for the Gaussian channel.

Describes the use of a parallel memory system for a SIMD architecture for signal processing. This paper develops the Chinese linear skewing scheme in order: (1) to have conflict-free access to vectors of interest in signal processing; (2) to allow a simple computation of local addresses; and (3) to use 100% of the memory capacity. With a linear skewing scheme, the vectors fetched from the parallel memory belong to a class of vectors called p-ordered vectors. For an odd number of memory banks, we present a new multidimensional alignment network which is able to unscramble all p-ordered vectors and which has a topology that is easy to implement.>