The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing.

As the industry advances towards smaller geometries for integrated circuits (ICs), internal cell defects have become increasingly crucial to address. Cell-Aware Testing (CAT) has emerged as the industry standard for achieving the high-quality levels required in modern ICs, as it explicitly targets intra-cell defects. However, the comprehensive defect coverage provided by CAT can result in a high test pattern count, which directly impacts test time and production costs.This paper proposes two complementary methodologies to optimize the cell library characterization phase by leveraging weak detections to maximize the number of Don’t Cares (DCs) and equivalent defects. The proposal produces an optimized Defect Detection Matrix (DDM) for the library, which is then used by the ATPG for pattern generation at the design level.The methodologies have been validated by running CAT ATPG for five different designs, using a 65nm cell library characterized with the proposed approach. The experimental results show that using the optimized DDMs reduces the number of patterns by an average of 8% and the pattern generation time by 11%, depending on the methodology used and the circuit analyzed.

Stress testing becomes more and more important to excite latent defects and reduce the infant mortality of manufactured ICs. Since no specific stress model exists in the DFT flow, toggle, IDDQ or random tests are typically used to create activity in the design and thus induce stress on the transistors. However, these kinds of tests are not accurate enough since they are mostly generated on the logical gate-level.This paper introduces a Cell-aware Transistor State Stress Model (TSSM) and a methodology to create a stress view for cell libraries as well as an application flow to assess the quality of the stress test patterns. During this flow, the TSSM can be dynamically configured and adapted to technology needs. This new flow uses this cell-aware stress view during simulation to provide a stress coverage of the test set. Experiments show the quality of different test sets and their ability to adapt to different model configurations.

Achieving zero defects has historically relied on port-level test-coverage (TC) from traditional scan Stuck-At and Transition-Delay tests. Defect-Oriented tests from Siemens showed a way detecting more defects and to measure test coverage using layout-based Total Critical Area. With the ever-shrinking process nodes, the BEOL layers are closer together and the redundancy factor of vias, especially the lower VIA layers has been dropping down significantly. Internal studies from quality and reliability failures confirmed non-redundant (NR) VIA defects that escaped all traditional detailed test coverage analysis. This motivated us to develop a new industry first per-layer NR VIA fault model extraction flow, which enabled us to successfully quantify NR VIA TC for sets of scan ATPG tests running in production test program. Details of a case study using new fault extraction and fault simulation flow to quantify per-layer NR VIA TC will be discussed in this paper.

As the manufactural technologies are moving to deep sub-micron process, the defects inside the design library cells occur more often during manufacture. Cell-Aware Testing (CAT) had been proposed to improve the test quality on detecting the cell internal defects. In CAT, the analog simulator is used to simulate the cell input combinations exhaustively for every defect to identify all the cell input combinations that detect the defects in the cells. However, it becomes less practical to handle the complex cells with large number of inputs and to consider multiple capture cycles because of the computational complexity of the analog simulation when processing the extremely large number of the input combinations. In this paper, we propose to model the design library cells as the ATPG library cells at the transistor level such that the existing ATPG tools can be used to generate the exhaustive test sets for every cell internal defect more efficiently. The generated test patterns are further divided into the hard-detection set and the soft-detection set. Only the test patterns from the soft-detection set need to be simulated by the analog simulator to verify the capability and the confidence level on detecting the defect. Using the proposed method can dramatically speed up the time-consuming step in the CAT flow, that is, for every defect to identify all input combinations that detect the defect through the analog simulation.

This article describes a defect-oriented test (DOT) approach, which enables a complete physical defect-based automatic test pattern generation (ATPG) for the digital logic area of CMOS-based designs. Total critical area (TCA)-based methods are presented for the generation of needed DOT views to enable the generation of complete DOT-based patterns for detecting all cell-internal and as well all cell-external physical defects. The major aim of these new methods and patterns is to further reduce the defect rate of manufactured ICs, in addition to what is already achieved with traditional and cell-aware test (CAT) fault models. We present test results, including achieved defect rate reduction in defective parts per million (DPPM), from a large 14-nm FinFET design, including a correlation to system-level-test (SLT) fails. For a second, mature 160-nm automotive mixed-signal sensor we present high-volume production test results, again measured in DPPM, and we provide test coverage figures moving away from counting detected faults to calculating detected TCA which is reported as the chip level TCA coverage.

This paper presents DPPM reduction results achieved with new Defect Oriented Test (DOT) methods/patterns applied to designs manufactured in advanced FinFET technologies. Focus of this paper is on Timing-Aware Cell-Aware Test (TA-CAT) patterns targeting small-delay defects of FinFET transistors, and a new DOT method which explicitly targets chip layout dependent cell-neighborhood defects. Test results from traditional Stuck-at/Transition patterns, from traditional CAT patterns, from TA-CAT patterns, and as well from cell-neighborhood patterns, applied to FinFET technology designs, will be presented in this paper. In addition, a correlation to System-Level-Test fails will be discussed.

High quality is an absolute necessity for automotive designs. This paper describes an approach to improve the overall defect coverage for CMOS-based high quality automotive designs. We present results from a cell-aware (CA) characterization flow for 216 cells, the pattern generation flow for a 130nm smart power design, and high-volume production test results achieved after testing multimillion parts. The idea behind CA tests is to detect cell-internal (CI) bridges, opens, leaking and high resistive transistor defects which are undetected with state-of-the-art tests. The production test results have shown that the CA tests detect various failing parts during a first wafer sort test which still resulted into unique failing parts after a second wafer sort test done at a different temperature and with additional tests. The obtained results encouraged us to continue this work beyond this paper to run further experiments with the final goal to eliminate the stuck-at (SA) and transition delay (TR) test by simultaneously improving the quality with CA tests which are a superset of SA and TR tests.

This paper describes the new cell-aware test (CAT) approach, which enables a transistor-level and defect-based ATPG on full CMOS-based designs to significantly reduce the defect rate of manufactured ICs, including FinFET technologies. We present results from a defect-oriented CAT fault model generation for 1,940 standard library cells, as well as the application of CAT to several industrial designs. We present high volume production test results from a 32 nm notebook processor and from a 350 nm automotive design, including the achieved defect rate reduction in defective-parts-per-million. We also present CAT diagnosis and physical failure analysis results from one failing part and give an outlook for using the functionality for quickly ramping up the yield in advanced technology nodes.

Numerous new multi-conditional fault models have been proposed in the last years. In combination with the increasing complexity of today's designs these new fault models cause a tremendous increases of the ATPG-runtime. In this paper we present a novel fault collapsing scheme for multi-conditional faults. The objective is to significantly reduce the fault set and hence reduce runtime for ATPG and fault diagnosis. The collapsing technique consists of three individual collapsing stages, which are individually discussed and evaluated. Additionally we provide an extensive set of experimental results including runtimes of a state-of-the-art ATPG-tool applied on a set of large industrial designs. We will demonstrate that the achieved reduction of up to 48% of the number of faults also reduces the ATPG runtime significantly.

The test set size is a highly important factor in the post-production test of circuits. A high pattern count in the test set leads to long test application time and exorbitant test costs. We propose a new test generation approach which has the ability to reduce the test set size significantly. In contrast to previous SAT-based ATPG techniques which were focused on dealing with hard single faults, the proposed approach employs the robustness of SAT-solvers to primarily push test compaction. Furthermore, a concept is introduced how the novel technique can be flexibly integrated into an existing industrial flow to reduce the pattern count. Experimental results on large industrial circuits show that the approach is able to reduce the pattern count of up to 63% compared to state-of-the-art dynamic compaction techniques.

This paper presents a highly robust approach to exactly analyze signal probabilities of Weighted Random Logic (WRL) BIST structures. WRL BIST structures are implemented in modern CMOS designs to ensure high defect coverage for example during on-line in-system tests, which are executed periodically in safety applications as needed in automotive designs. Furthermore the paper describes a novel design flow which automatically identifies and evaluates WRL BIST structures in large industrial designs. The complete design flow from calculating the weighted random logic up to its automatic identification and evaluation in pre- and post-layout netlists is discussed in detail. The effectiveness of the new approach has been evaluated on 10 industrial designs and various other test cases. The results show that the memory consumption of the proposed technique does not grow despite of an immense increase of the circuit size.

This paper describes a new approach for significantly improving overall defect coverage for CMOS-based designs. We present results from a defect-oriented cell-aware (CA) library characterization and pattern-generation flow and its application to 1,900 cells of a 32-nm technology. The CA flow enabled us to detect cell-internal bridges and opens that caused static, gross-delay, and small-delay defects. We present highvolume production test results from a 32-nm notebook processor to which CA test patterns were applied, including the defect rate reduction in PPM that was achieved after testing 800,000 parts. We also present cell-internal diagnosis and physical failure analysis results from one failing part.

This paper focuses on a new approach to significantly improve the overall defect coverage for CMOS-based designs with the final goal to eliminate any system-level test. This methodology describes the pattern generation flow for detecting cell-internal small-delay defects caused by cell-internal resistive bridges. Results have been evaluated on 1,900 library cells of a 32-nm technology. First production test results are presented from evaluating additional defect detections achieved with different fault models on a 45-nm design.

Industry is facing very high quality requirements for today's and tomorrow's ICs. Especially in the automotive market these quality requirements need to be fulfilled. To achieve this we need to improve currently used test methods and fault models to improve the overall defect coverage. This paper presents two new methodologies to significantly improve this situation. One method will focus on cell-internal Bridges over a wide range of Bridge resistor values and the second method concentrates on library cell-internal high-resistive Open defects. The fault models used during the ATPG are enhanced to directly target the layout-based intra-cell Open and Bridge defects. Both methods have been evaluated on 1500 library cells of a 65nm technology. In addition the wide range of intracell Bridges has been evaluated on 10 real industrial designs with up to 60 million faults. Various results are presented from all 1500 library cells and from the 10 industrial designs as well.

Industry is facing increasingly tougher quality requirements for more complex ICs. To meet these quality requirements we need to improve the defect coverage. This paper presents a new methodology to significantly increase the defect coverage of the test patterns generated by ATPG tools. The fault model used during the ATPG is enhanced to directly target layout-based intra-cell faults. In contrast to previous techniques, such as gate-exhaustive, N-detect, or embedded-multi-detect, which either are too complex for real-world designs or merely improve the probability of detecting intra-cell defects, the new approach targets the actual root causes of intra-cell defects. The newly proposed cell-aware-methodology has been evaluated for 90 nm and 65 nm technologies on 1671 library cells and on 10 real industrial designs with up to 50 million faults. The experimental results show an average increase of 1.2% in defect coverage and a reduction of 420 ppm in escape rate for a 50 mm2design.

Programmable mixed-mode BIST schemes combine pseudo-random pattern testing and deterministic test. This paper presents a synthesis technique for a mixed-mode BIST scheme which is able to exploit the regularities of a deterministic test pattern set for minimizing the hardware overhead and memory requirements. The scheme saves more than 50% hardware costs compared with the best schemes known so far while complete programmability is still preserved.

Due to the rapidly growing size of integrated circuits, there is a need for new algorithms for automatic test pattern generation (ATPG). While classical algorithms reach their limit, there have been recent advances in algorithms to solve Boolean Satisfiability (SAT). Because Boolean SAT solvers are working on conjunctive normal forms (CNFs), the problem has to be transformed. During transformation, relevant information about the problem might get lost and, therefore, is not available in the solving process. In this paper, we present a technique that applies structural knowledge about the circuit during the transformation. As a result, the size of the problem instances decreases, as well as the run time of the ATPG process. The technique was implemented, and experimental results are presented. The approach was combined with the ATPG framework of NXP Semiconductors. It is shown that the overall performance of an industrial framework can significantly be improved. Further experiments show the benefits with regard to the efficiency and robustness of the combined approach.

Despite the recent advances in ATPG technology computing test patterns for state-of-the-art industrial designs can demand an enormous amount of computation time. Numerous structural techniques were presented to reduce the search space and hence the runtime of state-of-the-art ATPG tools. Absolute dominators introduced by Kirkland and Mercer proved to be useful for finding mandatory observation nodes in a combinational circuit. A mandatory observation node denotes a gate which must be visited in order to propagate a fault to at least one primary output. Unfortunately their algorithm to compute absolute dominators does not scale well on large industrial designs. In this paper we propose a new algorithm to find absolute dominators in circuit graphs. The experimental results show a significant performance improvement with respect to runtime and memory consumption. The achieved speedup of three orders of magnitude on several designs enables the computation of absolute dominators in large industrial circuits in less than a second.

The demand for higher quality requires more effective testing to filter out the bad devices. It is already known that multi-detection of single stuck-at faults results in more fortuitous detections of defects not behaving as stuck-at faults, which increases the test quality. Existing multi-detect tests, i.e., the well-known n-detect tests, suffer from significant test size increases. This paper shows that embedding multi-detection of faults within regular ATPG patterns results in a higher quality without a significant increase in test set size. High-volume silicon measurement results demonstrate that embedded multi-detect tests detect 2.3% to 4.7% more defective devices than conventional single-detect stuck-at tests.

In this paper, we propose a new programmable deterministic built-in self-Test (BIST) method that requires significantly lower storage for deterministic patterns than existing programmable methods and provides high flexibility for test engineering in both internal and external test. Theoretical analysis suggests that significantly more care bits can be encoded in the seed of a linear feedback shift register (LFSR), if a limited number of conflicting equations is ignored in the employed linear equation system. The ignored care bits are separately embedded into the LFSR pattern. In contrast to known deterministic BIST schemes based on test set embedding, the embedding logic function is not hardwired. Instead, this information is stored in memory using a special compression and decompression method. Experiments for benchmark circuits and industrial designs demonstrate that the approach has considerably higher overall coding efficiency than the existing methods.

Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead to functional failures. Therefore, dynamic fault models like the path delay fault model (PDFM) have become more important in the last years. At the same time, classical algorithms for test pattern generation reach their limits due to the steadily increasing complexity of modern circuits. In this work, a SAT-based approach to calculate robust and non-robust test patterns for path delay faults (PDF) is presented. In contrast to previous approaches, the sequential behavior of a circuit is modeled adequately. Moreover, tri-state elements and environment constraints that occur in industrial practice can be handled. The encoding to apply a Boolean SAT solver for this problem is motivated and explained in detail. Experimental results for large industrial circuits show the efficiency of this approach.

This paper shows that accurate fault detection and diagnosis are possible when applying a parity tree for space compaction of test responses and continuously observing the parity-tree output. We exploit that each set of faults results in a unique parity-tree output sequence that can be used as a unique fault signature for truly accurate fault detection and diagnosis. Our theoretical analysis shows that probabilities for fault cancellation and fault aliasing are extremely low and decrease with circuit size. Experimental results show that for a typical scan chain architecture in large industrial circuits, fault coverage is not affected by parity-tree space compaction for up to 256 scan chains, while diagnostic resolution is reduced by only 1% to 2%.