In order to nd a clue to effectively introducing and utilizing new technology in improving software development process, we analyze and visualize the in-degree centrality of the process area networks in terms of the related process areas in CMMI-DEV. By visualizing the results of in-degree centrality analysis, we can have a perspective of process improvement in using advanced technology.

Multiprocessing and multithreading increase frequencies of thread schedulings and context switches. Context switches can decrease the system throughput because they disturb locality of references and cause cache misses such as translation lookaside buffer (TLB), LI, and L2 misses. To reduce the overhead due to context switches, we focus on the advantage of threads which share the same memory address space (sibling threads). In switching sibling threads, the operating system (OS) does not have to switch their memory address spaces. Thus, we can omit a part of switching procedure and expect an efficient use of memory hierarchy. To utilize this advantage, we have proposed a context aware scheduler, which aggregates sibling threads. By using our scheduler, we can expect to reduce the switches of memory address spaces in executing multithreaded applications. Because switching memory address spaces results in TLB flushes on some kinds of processors, our scheduler can be effective in reducing TLB misses on such platforms. In this paper, we evaluate the effect of our context aware scheduler on reducing TLB misses. For this purpose, we run several multithreaded applications simultaneously with our context aware scheduler and measure the number of TLB misses. From these experiments, we conclude that our context aware scheduler is effective in reducing TLB misses and contributes to enhance the system throughput without imposing the degradation of throughput on any application.

Fine-grained multithreading based on a natural model, such as dataflow model, is promising in achieving high efficiency and high programming productivity. In this paper, we discuss operating system issues for fine-grained multithread programs. We are developing an operating system called CEFOS based on a dataflow based computation model. A program on CEFOS consists of zero-wait threads which run to completion without suspension once started. Firing control among such threads is performed in a dataflow manner along with continuation relations in the program. Target platforms include fuce processor, which is dedicated to fine-grained multithreading, and commodity processors such as Intel x86. In this paper, after introducing our basic model and our operating system model, we discuss implementation issues on fuce and commodity platforms. The evaluation results indicate that our approach on commodity platforms is effective in reducing overheads while our approach on a special architecture naturally exploit parallelism even in I/O handling.

Optimal control sets are defined as sets with a smaller cardinality than the cardinality of the set of controlled transitions and obtained when modeling control systems with a multiple and simultaneous control (MSC) approach using Controlled Dan/Petri nets+(Ctrl D/PN+); optimal and non-redundant control sets are defined as optimal sets without controllers that result redundantly in terms of a set of admissible markings with specific characteristics. In this paper we explain how to find the optimal an non-redundant set of controls in control systems modeled with Ctrl D/PN+and present the net structure ∑na(q)−yto model the MSC-logic.

Latency, caused by remote memory access and remote procedure call, is one of the most serious problems in massively parallel computers. In order to eliminate the processors' idle time caused by these latencies, processors must perform fast context switching among fine-grain concurrent processes. In this paper, we propose a processor architecture, called Datarol-II, that promotes efficient fine-grain multi-thread execution by performing fast context switching among fine-grain concurrent processes. In the Datarol-II processor, an implicit register load/store mechanism is embedded in the execution pipeline in order to reduce memory access overhead caused by context switching. In order to reduce local memory access latency, a two-level hierarchical memory system and a load control mechanism are also introduced. We describe the Datarol-II processor architecture, and show its evaluation results.>

Article A dataflow language with object-based extension and its implementation on a commercially available parallel machine Share on Authors: Shigeru Kusakabe Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, Japan Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, JapanView Profile , Taku Nagai Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, Japan Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, JapanView Profile , Yoshihiro Yamashita Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, Japan Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, JapanView Profile , Rin-ichiro Taniguchi Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, Japan Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, JapanView Profile , Makoto Amamiya Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, Japan Dept.of Information Systems, Kyushu University, Kasuga Fukuoka 816, JapanView Profile Authors Info & Claims ICS '95: Proceedings of the 9th international conference on SupercomputingJuly 1995 Pages 308–317https://doi.org/10.1145/224538.224575Online:03 July 1995Publication History 8citation202DownloadsMetricsTotal Citations8Total Downloads202Last 12 Months0Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access