Demo Data from VLDB 2026 / reviewers in the wild / expert
Matthew Ramsay
dblp:07/2427
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Performance modeling and evaluation · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Performance modeling and evaluation
performance prediction |
0.1 | 1 | 2006 | A case study in top-down performance estimation for a large-scale parallel application · PPoPP 2006 |
Performance modeling and evaluation › tracing
instruction tracing |
0.0 | 1 | 2006 | A case study in top-down performance estimation for a large-scale parallel application · PPoPP 2006 |
Methods — techniques the papers use, named apart from their topics
scalability modeling · 0.1component simulation · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2007 | Characteristics of workloads used in high performance and technical computingabstractThis paper provides a systematic comparison of various characteristics of computationally-intensive workloads. Our analysis focuses on standard HPC benchmarks and representative applications. For the selected workloads we provide a wide range of characterizations based on instruction tracing and hardware counter measurements. Razvan Cheveresan, Matthew Ramsay, Chris Feucht, Ilya Sharapov |
ICS | 2 |
| 2006 | A case study in top-down performance estimation for a large-scale parallel applicationabstractThis work presents a general methodology for estimating the performance of an HPC workload when running on a future hardware architecture. Further, it demonstrates the methodology by estimating the performance of a significant scientific application -- the Gyrokinetic Toroidal Code (GTC) -- when executing on Sun's proposed next-generation petascale computer architecture.For GTC, we identify the important phases of the iteration and perform low-level analysis that includes instruction tracing and component simulations of processor and memory systems. Low-level analysis is complemented with scalability estimates based on modeling MPI, OpenMP and I/O activity in the code. The work's approach permits accurate end-to-end performance projections from the microarchitecture level to the petascale. Ilya Sharapov, Robert Kroeger, Guy Delamarter, Razvan Cheveresan, Matthew Ramsay |
PPoPP | 5 |