Gurgen Harutunyan

VLDB 2026 Research / reviewers in the wild / expert

dblp:07/2799 · also Gurgen Harutyunyan · DBLP profile ↗

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43ranked-venue papers

12as first author

15since 2021 · last 2026

0000-0002-9709-8336ORCID · reported

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 43 · 12 first-author · 15 since 2021Software engineering, systems software and programming languages · 5 · 1 first-author · 1 since 2021

Year	Publication	Venue	Position
2026	On-Chip Sensor with Programmable Delay Logic to Monitor Memory Aging Evolution Fabian Vargas 0001, Vache Galstyan, Gurgen Harutunyan, Yervant Zorian	DDECS	3
2025	European Test Symposium Teams: an Anniversary Snapshot abstract The IEEE European Test Symposium (ETS) has been facilitating progress in electronic systems testing since its launch in 1996. On the occasion of its 30th anniversary, this collaborative paper gathers sections by 21 ETS teams to outline their influential ideas and milestones. Each team’s section highlights historical perspective, current research, frameworks and projects as well as forward-looking research agendas in the area of electronic-based circuits and systems testing, reliability, safety, security and validation. This anniversary summary documents how research of various ETS teams, exemplifying the test community, has been evolving and transitioning from concepts to practical standards and Electronic Design Automation (EDA) tools and flows. This legacy is a strong base to drive the next generation of advances in electronic systems testing. Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, Iulia Stefan, Ovidiu Stan, Cosmina Corches, Zebo Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, Po-Yao Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi 0002, Stefano Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. D. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, Patrick Girard 0001, Marcello Traiola, Arnaud Virazel, Fernando Santos 0001, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Veiras Bolzani, Milos Krstic, Marko S. Andjelkovic, Fabian Vargas 0001, Grigor Tshagharyan, Gurgen Harutunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, Anurup Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zainalabedin Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand	ETS	56
2025	Analysis and Mitigation of Radiation Effects in SRAM-based Register Files Surendra Hemaram, Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi Baradaran Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ETS	9
2025	Leveraging UCIe Interface for Silicon Health & Reliabiilty of Chiplets in a 3D Stack abstract The exponential growth in test data volume for modern Systems-on-Chip (SoCs), combined with a decreasing number of available test pins, has led to increased test time and complexity. Simultaneously, the industry’s drive for higher quality and lower Defective Parts Per Million (DPPM) necessitates continuous monitoring, testing, and repair Silicon Lifecycle Management (SLM). The advent of multi-die packaging technologies, such as 2.5D and 3D stacked integration, further exacerbates these challenges by introducing additional layers of interconnect and access constraints.Universal Chiplet Interconnect Express (UCIe) emerges as a compelling solution for delivering test content to all constituent dies at-speed, post-packaging. UCIe enables seamless test access across various lifecycle stages, including wafer sort, package test, System Level Test (SLT), and In-System Test (IST).This paper introduces a silicon-proven methodology that integrates the UCIe protocol with advanced SLM techniques to address the critical challenges of access, test, measurement and repair in complex multi-die SoC designs. Silicon results from test vehicles fabricated on TSMC N3P process with CoWoS-S packaging demonstrate complete interconnect, logic, and memory test, repair, and monitoring capabilities, validating the effectiveness and scalability of the proposed approach for next- - generation multi-die systems. Sandeep Kumar Goel, Ankita Patidar, Stanley John, Frank Lee 0004, Min-Jer Wang, Daniel F. J. Yang, Yervant Zorian, Manish Arora, Firooz Massoudi, Shaan Awasthi, Stelios Balalis, Velmurugan Pathervellaichamy, Bharath Shankaranarayanan, Narasimhalu Raju, Gurgen Harutunyan, Grigor Tshagharyan, Vahagn Hovakimyan, Arman Karagyozyan, Alvina Manucharyan	ITC	15
2024	On-Chip Sensor to Monitor Aging Evolution in FinFET-Based Memories abstract Aging of electronics can be caused by various physical mechanisms, including bias temperature instability (BTI), hot carrier injection (HCI), time-dependent dielectric breakdown (TDDB) and electromigration (EM). Aging phenomena may lead to a degradation of performance and reliability of an electronic system, hence limiting its expected lifetime. The goal of this paper is twofold. First, it presents an advanced, miniature design of an aging sensor; second, it shows how this sensor is integrated with a commercial 5 nm FinFET-based SRAM IP core. The sensor is implemented with a small number of logic gates, resulting in negligible overhead in area, power and delay. The sensor is also equipped with power gating capability. Thus, during idle time, the sensor is temporarily disconnected from the power supply lines to prevent aging of its transistors. Experimental results based on extensive SPICE simulations demonstrate that this approach is able to detect even the slight increase in memory response time due to aging much earlier than a functional error is observed at the memory output. This solution enables mission-mode monitoring of memory operation, which is a critical aspect of silicon lifecycle management (SLM) framework. Fabian Vargas 0001, Vache Galstyan, Gurgen Harutunyan, Yervant Zorian	IOLTS	3
2024	Testing for aging in advanced SRAM: From front end of the line transistors to back end of the line interconnects abstract The long-term reliability of Static Random Access Memory (SRAM) is crucial for safety-critical applications, such as those in the automotive industry. In the front-end-of-line (FEoL), the transistor elements are susceptible to negative bias temperature instability (NBTI), while in the back-end-of-line (BEoL) the interconnects are susceptible to electromigration (EM), especially in scaled technology nodes. To meet safety-critical standards, it is essential to investigate the combined aging mechanisms within the SRAM array and to develop effective testing methodologies during the operational lifetime of the system. Such methodologies are also crucial for enabling the early detection of in-field failures. In this paper, a precise aging model is presented that extends the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model and includes physical modeling for EM. This approach provides insights into the combined effects of NBTI and EM on the degradation of SRAM writability, considering the entire SRAM subarray, including the bit-cell array and peripheral circuits in Fin Field-Effect Transistors (FinFET) technology. Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi Baradaran Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ITC	8
2024	Addressing the Combined Effect of Transistor and Interconnect Aging in SRAM towards Silicon Lifecycle Management abstract The long-term reliability of the Static Random Access Memory (SRAM) module, as an important component of computing architectures, is crucial for safety-critical applications such as automotive. In the front end of the line (FEoL), the transistor elements are vulnerable to negative bias temperature instability (NBTI), while the back end of the line (BEoL) interconnect is prone to electromigration (EM). Complying with safety-critical standards as part of silicon lifecycle management (SLM) infrastructure requires an understanding of the combined aging mechanisms of transistors and interconnects in SRAM. Moreover, a precise aging model is a prerequisite for effective aging testing and mitigation strategies. For this aim, we augment the Technology Computer-Aided Design (TCAD) transistor model with a detailed NBTI model at the FEoL, and use measurement-calibrated physical modeling of EM at the BEoL, to create an integrated analysis that can provide deeper insights into the individual and combined effects of NBTI and EM for SRAM operation. Our findings reveal the mutual acceleration of delay faults and hard stuck-at faults caused by NBTI and EM in SRAM, offering a precise methodology for estimating the time to failure under these conditions. Mahta Mayahinia, Christian Weis, Norbert Wehn, Mehdi Baradaran Tahoori, Sani R. Nassif, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	VTS	8
2023	On-chip Electromigration Sensor for Silicon Lifecycle Management of Nanoscale VLSI abstract The advanced CMOS technology with smaller feature sizes has greatly improved the performance, energy, and area efficiency of the VLSI systems. Alongside the transistor feature size, back-end-of-the-line (BEoL) interconnects are also shrinking which makes them susceptible to electromigration (EM). Current density and temperature have decisive impacts on the EM profile of the BEoL interconnects, which themselves are highly affected by the running workload. Hence, the actual degradation and the remaining lifetime of a VLSI system are impacted by its usage scenarios. Therefore, in-field monitoring of the chip usage can predict failures before they happen and cause catastrophic failures, and in addition, provide an accurate estimate of the remaining useful lifetime to schedule preventive maintenance. In this work, we propose a simple yet effective on-chip EM sensor that can be embedded as a part of chip silicon lifecycle management (SLM) infrastructure. Further, we show how our proposed EM sensor can be effectively leveraged as a general sensor for the estimation of the remaining useful lifetime of the chip. The simulation results for the 5nm realistic SRAM design show that the power overhead of the proposed sensor is only 0.00365% of the SRAM module with a negligible area overhead. Mahta Mayahinia, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ETS	4
2023	Utilizing ECC Analytics to Improve Memory Lifecycle Management abstract With reliability being a critical factor in many applications today, in-system failure detection and correction is a key requirement for ensuring smooth operation in the field. For memory components that occupy the majority of the chip space, this is commonly accomplished with the help of error correcting codes (ECC). However, ECC can offer much more than plain error detection and correction. In particular, the paper describes some of the most common use cases of ECC that help not only to monitor memory health but also to extend its service lifetime by analyzing ECC data over time. Costas Argyrides, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ITC	3
2023	SLM Subsystem for Automotive SoC: Case Study on Path Margin Monitor abstract As the size and complexity of System-on-Chip (SoC) continue to grow, product performance and durability requirements have also become a vital part of chip design. By deploying monitors and structures built into the silicon design, we can obtain real-time data on the performance of the chip, which in turn can be used to study the health of the silicon and predict its degradation. This is a particularly important requirement for safety-critical applications such as automotive. In this paper, a case study of Path Margin Monitor (PMM) is presented as part of an automotive SoC subsystem that can monitor the functional paths of silicon in real-time throughout the entire silicon lifecycle. Kranthi Kandula, Ramalingam Kolisetti, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ITC	4
2023	Overcoming Embedded Memory Test & Repair Challenges in the Gate-All-Around Era abstract The paper discusses the challenges that memory testing faces in the era of Gate-All-Around transistor technology and proposes a solution concept to overcome them. With the transition from two-dimensional to three-dimensional transistors, and in particular with the advent of FinFET, many new factors have entered the scene, creating a need for new testing techniques capable of coping with the complexity of novel memory designs. However, the end of the FinFET era and the beginning of a new Gate-All-Around design paradigm means that these methods need to be revisited to ensure they remain effective and in line with the latest transistor technologies that are contenders to replace FinFET. The paper assesses the test challenges associated with the Gate-All-Around technology and proposes a solution concept that sets a vector for a thorough investigation of underlying defects, fault modeling, and the development of efficient test and repair algorithms. Artur Ghukasyan, Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	VTS	3
2023	An Efficient External Memory Test Solution: Case Study for HPC Application abstract An increasing amount of data are being stored and processed by data centers every day for various commercial and industrial applications. For such large-scale systems dealing with enormous volumes of data, utilization of Dynamic Random-Access Memories (DRAM), integrated into horizontal or vertical stacks, has been proven to be the ideal solution in terms of area vs performance. At-speed test and repair in these stacks of DRAM memories requires complex solutions given the various lifecycle stages the memories go through. In this paper an efficient Built-In Self-Test (BIST) concept is proposed, focusing on both the in-system and production aspects of the test solution. It is demonstrated for a real-life High-Performance Computing (HPC) application. Keqing Ouyang, Minqiang Peng, Yunnong Zhu, Kang Qi, Grigor Tshagharyan, Gurgen Harutunyan, Isaac Wang	VTS	7
2022	A Novel Protection Technique for Embedded Memories with Optimized PPA abstract In today's complex applications, reliability is becoming an increasingly important issue, and one of the most attractive solutions for dealing with in-system failures is error correcting code (ECC). In this paper a novel protection technique is proposed based on an advanced ECC solution that takes into account the level of memory utilization and uses various ECC configurations to optimize power consumption, performance and area. The experimental results demonstrate the effectiveness of the proposed solution. Costas Argyrides, Vilas Sridharan, Hayk Danoyan, Gurgen Harutunyan, Yervant Zorian	ITC	4
2022	An Efficient Test Strategy for Detection of Electromigration Impact in Advanced FinFET Memories abstract Moving to more advanced CMOS technologies can improve the performance and energy efficiency of the VLSI systems, including the static RAM (SRAM) as one of the most demanding memory elements of the modern computer systems. However, the long-term reliability of the SRAM is also important and needs to be carefully considered. This is particularly of utmost importance in safety critical systems, including automotive, with stringent requirements for in-field testing. In advanced technology nodes, the interconnects are designed in a tighter pitch-size, which result in an increase in the current density. Moreover, due to the higher chip complexity, the operating temperature is typically higher. Both the high current density and high temperature exacerbate the electromigration (EM) phenomenon in interconnects, which eventually leads to resistance increase and timing faults. This negatively influences the long-term reliability of the system. Because of the EM, SRAM-based memory modules may undergo field failure, such as read or write faults. To avoid functional safety violation, early detection and prediction of the EM is crucial. In this work, we propose an optimized EM test methodology which is able to predict the effect of EM up to 9.7 months earlier before it leads to failures in normal functional mode. Mahta Mayahinia, Mehdi Baradaran Tahoori, Gurgen Harutunyan, Grigor Tshagharyan, Karen Amirkhanyan	ITC	3
2022	Innovative Practices Track: What's Next for Automotive: Where and How to Improve Field Test and Enhance SoC Safety abstract Safety is established as one of top priorities for Automotive SoCs along with security and reliability. However, testing is also known to play a crucial role since the degree of safety indirectly depends on the quality of test solution employed by SoC. In recent years, numerous studies and a large number of papers have been published on this topic, which seemed to form the necessary concepts and requirements for test solutions to achieve the desired level of functional safety. Among others, they introduced the concepts such as power-on self-test, check the checkers, mission mode test, periodic self-test, and so on. At this point, the question naturally arises whether we are hitting the limit, or we are still halfway there, and there is still room to improve field test and further enhance safety. During this session, we will ask speakers who are renowned experts in the field to share their views on the future of automotive industry and what comes next in terms of functional safety. Minqiang Peng, Youfa Wu, Alex Yu, Grigor Tshagharyan, Costas Argyrides, Vilas Sridharan, Gurgen Harutunyan, Yervant Zorian	VTS	8
2020	Die-to-Die Testing and ECC Error Mitigation in Automotive and Industrial Safety Applications abstract Two significant trends can be nowadays seen in automotive and industrial applications: an increase of the amount of data that is stored and elaborated by those systems, thus requiring bigger on-board DRAMs (Dynamic Random Access Memories), and the strict demands for reliability and safety. Safety is ruled by standards, that impose requirements for acceptable FIT rate-one of the most common metrics used for quantitatively evaluating the effects of such errors. It is then relevant to investigate the errors that can occur in DRAMs and propose mitigation techniques to deal with them. In this paper, die-to-die testing scenario is considered, and a methodology is described for mitigating the effects of errors by using well-known Error Correcting Codes (ECC). An advanced ECC solution is then presented along with the infrastructure needed for effectively testing DRAMs, including soft errors and permanent faults. The FIT rates calculations are finally considered, together with examples and case studies illustrating the effectiveness of the proposed solution. Gabriele Boschi, Elisa Spano, Hayk T. Grigoryan, Gurgen Harutunyan	ITC	5
2020	Test and Diagnosis Solution for Functional Safety abstract This paper discusses the automotive requirements of ISO 26262 standard and its implication on conventional test and diagnosis flows. It presents a safety-oriented manufacturing test and diagnosis solution meeting automotive system-on-chip (SoC) requirements. The implementation details, automotive features and experimental results are described showing the effectiveness of the proposed solution. M. Casarsa, Gurgen Harutunyan, Yervant Zorian	ITC	2
2019	Memory FIT Rate Mitigation Technique for Automotive SoCs abstract This paper considers the reliability and safety issues in automotive applications which are of highest importance. FIT rate is one of the most common metrics used for quantitatively evaluating such issues. Strict requirements exist for acceptable FIT Rate in automotive applications. The problem of calculating the FIT rate at SoC level is considered in this paper and then it focuses on memories, which comprise a large part of current SoCs and have a great impact on the overall FIT rate. The vulnerability factors are considered, which help to get a better approximation of real-life situations. A methodology is presented for mitigating the effects of soft errors in memories via selective adoption of error detecting and correcting codes (ECC). Ways to calculate the FIT rate in the presence of ECC are considered and an advanced ECC solution is presented. Since using ECC increases the SoC area (extra logic and memory bits are needed) and decreases performance (delay in ECC logic that calculates / verifies the codes), a planning solution for choosing which memories should have ECC for optimal reliability/area is presented. Some experimental results are adduced to illustrate the effectiveness of the proposed techniques. Gabriele Boschi, Donato Luongo, Duccio Lazzarotti, Hanna Shaheen, Hayk T. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Yervant Zorian	ITC	6
2019	Innovative Practices on In-System Test and Reliability of Memories abstract This innovative practice session includes three presentations which discuss test and reliability issues and solutions for external and embedded memories. At speed test for external memories, memory array diagnosis and interconnect faults detection, as well as the peculiarities of supporting different memory IPs including DRAM and HBM2 are among the topics discussed. As for embedded memories, FIT rate calculation and mitigation methodology is presented which is shown to be critical for automotive SoCs. S. Bandyopadhyay, J. Mekkoth, Marc Hutner, Hayk T. Grigoryan, Samvel K. Shoukourian, Grigor Tshagharyan, Yervant Zorian, Gabriele Boschi, Duccio Lazzarotti, Donato Luongo, Hanna Shaheen, Gurgen Harutunyan	VTS	13
2019	Fault Awareness for Memory BIST Architecture Shaped by Multidimensional Prediction Mechanism abstract This paper introduces a novel solution for building fault aware memory built-in self-test infrastructure based on rules of fault periodicity and regularity in memories and test algorithms. These periodicity and regularity rules are described via special internal structures named fault periodicity table (FPT) and test algorithm template (TAT). Three dimensions of evolution are considered as inputs for forming the mentioned structures: memory cells, multidimensional memory circuits, and memory systems for systems-on-chip where memories are distributed in different subchips. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. FPT allows considering any large number of faults in one table while TAT allows constructing test algorithms without using test algorithm generation tools. Experimental results of the solution applied to both Planar-based (90/65/45/28 nm) and FinFET-based (16/10/7 nm) memory technologies are adduced also in this paper. Gurgen Harutunyan, Samvel K. Shoukourian, Yervant Zorian	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1
2018	Case Study and Advanced Functional Safety Solution for Automotive SoCs abstract In this paper, an efficient functional safety solution is presented to address the requirements mandated by ISO 26262 standard and to be used in automotive applications. This solution is validated on a comprehensive automotive SoC, which includes in it considerable amount of embedded memories, along with numerous logic and AMS IP blocks. The obtained results demonstrate the advantages and effectiveness of the proposed solution. M. Casarsa, Gurgen Harutunyan	ITC	2
2018	Advanced ECC-Based FIT Rate Mitigation Technique for Automotive SoCs abstract Automotive innovation is driving the need for built-in reliability, safety and security solutions and architectural design to mitigate emerging threats and, particularly, the number of possible sources affecting arisen failures. In other words, the problem can be stated as reduction of failure rate-one of the most common metrics used for reliability evaluation. Soft errors in memories will be considered in the paper. Their FIT rate is significantly more than the typical FIT rate for a hard reliability failure. A special technique is described to assess the soft error rate and to mitigate the effects of soft errors via error correcting codes (ECC). Ways to calculate the failure rate in the presence of ECC are considered jointly with different ECC solutions. Since ECC also incurs a significant area overhead, a problem arises how to choose memories in SoC which should have ECC in order to meet the reliability requirements and, at the same time, the area constraints. In this paper, an efficient ECC planning solution is presented to solve the problem. The experimental results are adduced which show the advantages of the proposed solution. Hayk T. Grigoryan, Samvel K. Shoukourian, Gurgen Harutunyan, Yervant Zorian, Costas Argyrides	ITC	3
2018	Advanced Uniformed Test Approach For Automotive SoCs abstract The fast growing Automotive SoC market presents new test challenges, combining traditional production requirements as well as new Functional Safety (FuSa) related aspects. In order to meet these challenges, an innovative approach must be introduced. This paper presents a detailed case study demonstrating typical Automotive SoC requirements, in addition to an advanced Uniformed Test Approach, specially tailored in order to fulfill them. Tal Kogan, Yehonatan Abotbol, Gabriele Boschi, Gurgen Harutunyan, N. Martirosyan, Yervant Zorian	ITC	4
2018	Defect injection, Fault Modeling and Test Algorithm Generation Methodology for STT-MRAM abstract Spin Transfer Torque Magnetic Random Access Memory (STT-MRAM) is a promising alternative technology for on-chip memories due to several advantages such as high density, non-volatility, scalability, high endurance and CMOS compatibility. Due to the emerging fabrication processes of magnetic layers in the fabrication of STTMRAM devices, they are more susceptible to manufacturing defects and have different failure mechanisms compared to conventional CMOS memories. This mandates specific fault modeling and development of proper test algorithms for high coverage testing of these memories in order to ensure correct functionality in the field. In this paper, a detailed defect injection is performed based on the magnetic devices and layout characteristics of STT-MRAM and unique fault models are constructed for these memories. Based on the derived fault models and behaviors, efficient test algorithms are developed to fully cover these faults. Sarath Mohanachandran Nair, Rajendra Bishnoi, Mehdi Baradaran Tahoori, Grigor Tshagharyan, Hayk T. Grigoryan, Gurgen Harutunyan, Yervant Zorian	ITC	6
2018	Modeling and Testing of Aging Faults in FinFET Memories for Automotive Applications abstract Automotive has become one of the most prevailing sectors of the modern semiconductor industry. Due to strict requirements for safety, reliability, and security the proposed test & repair solutions for automotive applications undergo a circumstantial verification before exploitation. Traditionally production defects and soft errors occurring in the operation mode were considered to be the main source of failures for System-on-Chips (SoC). Nevertheless, aging-induced faults especially in modern technology nodes also pose certain challenges for SoC lifetime and impact the overall Failure in Time (FIT) rate of the system. Meanwhile keeping hold of low FIT rate is one of the main criteria for reliability. In this paper, a comprehensive study on aging faults is conducted for FinFET memories and an efficient test & repair methodology is proposed that meets the automotive requirements and allows decreasing the FIT rate of the system. Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian, Anteneh Gebregiorgis, Mohammad Saber Golanbari, Rajendra Bishnoi, Mehdi Baradaran Tahoori	ITC	2
2018	Innovative practices on memory test practice abstract In this IP session, there will be 3 presentations focusing on the state-of-the-art memory test practices from tools and industrial implementation perspectives. The 1stpresentation will discuss the memory test strategies in the automotive space. The 2ndpresentation discusses memory tests strategies for enabling test cost reduction. The 3rdpresentation will discuss on array BIST and its presence and usage in various applications of the current generation designs. M. Casarsa, Gurgen Harutunyan, Kaitlyn Chen, Ramesh Sharma, Giri Podichetty, Martin Keim, Sreejit Chakravarty, Ramesh C. Tekumalla	VTS	2
2017	Advanced ECC solution for automotive SoCs abstract The modern automotive industry has entered an era where the tendencies are towards increased automation and connectivity. With every new generation, the proportion of electronics-controlled systems in the vehicles is steadily growing. In parallel the safety and reliability requirements to automobiles are becoming more stringent thus requiring more sophisticated approaches. The problem is complicated by the fact that automotive has started to use cutting-edge technologies whose maturity might not be always at high level. Thus, there is a need to ensure not only low DPPM during production mode but also high reliability during mission mode. This paper presents an advanced Error Correcting Codes (ECC) solution which ensures high level of single-bit and multi-bit error detection and correction for memories operating in mission mode. This solution addresses the main requirements posed by automotive industry as well as successfully passed ISO 26262 certification with ASIL-D grade. Hanna Shaheen, Gabriele Boschi, Gurgen Harutunyan, Yervant Zorian	IOLTS	3
2017	Advanced functional safety mechanisms for embedded memories and IPs in automotive SoCs abstract Given the fast growing complexity and miniaturization of automotive SoCs, this paper presents functional safety challenges and related solutions for such SoCs. The paper is based on ISO 26262 standard and shows experimental results on a SoC example to demonstrate the advantages of the proposed solutions. Tal Kogan, Yehonatan Abotbol, Gabriele Boschi, Gurgen Harutunyan, I. Kroul, Hanna Shaheen, Yervant Zorian	ITC	4
2017	An effective functional safety solution for automotive systems-on-chip abstract A functional safety solution based on multi-purpose built-in self-test and repair infrastructure for automotive SoCs is presented. This solution allows building a hierarchical network and managing it in multiple in-field test and repair modes. Grigor Tshagharyan, Gurgen Harutunyan, Yervant Zorian	ITC	2
2015	An effective embedded test & diagnosis solution for external memories abstract From a structural viewpoint, an external memory linked to a system-on-chip (SoC) via high speed I/Os is typically composed of one or more memory dies/chips that interact with SoC using high bandwidth. Though testing an external memory and its high speed interconnects has always been a challenge, nevertheless this challenge became more critical with the increased use of high density packages, such as 2.5D or 3D. Not only fault detection but also fault diagnosis is important for fault type and fault location identification in external memories. In this paper an effective embedded test and diagnosis solution for external memory array and interconnects is proposed. The paper presents a new taxonomy for fault classification and new fault detection and diagnosis algorithm identifying external memory fault types and their locations. Finally it describes a built-in self- test (BIST) implementation which was successfully applied to DDR4 SDRAM. Gurgen Harutunyan, Yervant Zorian	IOLTS	1
2015	Impact of parameter variations on FinFET faults abstract The technology shrinking strategy below 20nm feature sizes adopted by the giants of the nowadays semiconductor industry has boosted the research on FinFET which is considered as an alternative to the conventional planar technology. This paper presents a comprehensive study carried out for FinFET-based memories using an advanced flow for fault modeling and test algorithm generation. Using this flow it has been shown that parameter variation (of process, voltage, temperature, frequency) has a significant impact on the fault coverage when dealing with FinFET-specific faults. Gurgen Harutunyan, Grigor Tshagharyan, Yervant Zorian	VTS	1
2014	Fault modeling and test algorithm creation strategy for FinFET-based memories abstract FinFET transistors are playing an important role in modern technology that is rapidly growing. Embedded memories based on FinFET transistors lead to new defects that can require new embedded test and repair solution. To investigate FinFET-specific faults the existing models and detection techniques are not enough due to a special structure of FinFET transistors. This paper presents a new strategy for investigation of FinFET-specific faults. In addition to fault modeling, a new method is proposed for test algorithm synthesis. The proposed methodology is validated on several real FinFET-based embedded memory technologies. Moreover, new faults are identified that are specific only to FinFETs. Gurgen Harutunyan, Grigor Tshagharyan, Valery A. Vardanian, Yervant Zorian	VTS	1
2013	Integrating embedded test infrastructure in SRAM cores to detect aging abstract One of the most important phenomena degrading Nano-scale Static Random Access Memory (SRAM) reliability is related to Negative-Bias Temperature Instability (NBTI). This paper presents the integration of the OCAS (On-Chip Aging Sensor) approach in the design methodology of 28nm single-port SRAM cores. The goal is to enhance the current test and repair on-chip infrastructure to detect SRAM aging during system lifetime. OCAS is able to detect the aging state of a cell in the SRAM array. The strategy is based on the connection of one OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM content after testing. SPICE simulations allowed us to analyze the OCAS sensitivity to detect early aging states in this very deep submicron technology, as well as the area, power and performance penalties due to the sensor insertion. W. Prates, Letícia Maria Veiras Bolzani, Gurgen Harutunyan, A. Davtyan, Fabian Vargas 0001, Yervant Zorian	IOLTS	3
2013	An effective solution for building memory BIST infrastructure based on fault periodicity abstract This paper introduces a new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms. It is proposed to describe all the periodicity and regularity rules in a form of a special Fault Periodicity Table (FPT) and March Test Template (MTT). FPT allows considering any large number of faults in one table and MTT allows obtaining March tests without using special tools for their generation. Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	VTS	1
2012	A New Method for March Test Algorithm Generation and Its Application for Fault Detection in RAMs abstract In this paper, all linked and unlinked static and two-operation dynamic faults are considered. A classification for their description is introduced. To generate a test algorithm for detection of all the considered faults, it was shown that it is not an easy problem. For this purpose, a new structure-oriented method is developed. Based on the proposed method, an efficient test algorithm March LSD of complexity 75N is generated for the detection of the considered linked static and dynamic faults. Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1
2011	A Robust Solution for Embedded Memory Test and Repair abstract This paper presents a robust solution for test and repair of embedded memories. The STAR (Self-Test and Repair) Memory System solution is developed within Synopsys Design Ware allowing users to create, integrate and verify embedded memory test and repair IP in system on chips. The key components and features of the SMS are discussed. K. Darbinyan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	Asian Test Symposium	2
2011	Generic BIST architecture for testing of content addressable memories abstract Minimal March test algorithms are developed for single-port binary and ternary content addressable memories (CAMs). Based on these test algorithms a built-in-self-test (BIST) architecture for testing of CAMs is proposed. It is an extension of an existing BIST architecture for testing of static random access memories (SRAMs) and read-only memories (ROMs). This generic BIST architecture additionally supports the following important CAM specific features: power buffer-zones, multicycle compare operations, half/quarter words and walking patterns. Hayk T. Grigoryan, Gurgen Harutunyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	IOLTS	2
2011	Symmetry Measure for Memory Test and Its Application in BIST Optimization Gurgen Harutunyan, Aram Hakhumyan, Samvel K. Shoukourian, Valery A. Vardanian, Yervant Zorian	J. Electron. Test.	1
2008	An Efficient March-Based Three-Phase Fault Location and Full Diagnosis Algorithm for Realistic Two-Operation Dynamic Faults in Random Access Memories abstract Previously, a minimal algorithm of length 70 N, N is the number of memory bits, was proposed for a subclass of dynamic faults. In this paper, a March-based fault location and full diagnosis algorithm of complexity 88 N+29 is proposed for the same subclass of dynamic faults in bit-oriented SRAMs. Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	VTS	1
2007	Minimal March Tests for Detection of Dynamic Faults in Random Access Memories Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	J. Electron. Test.	1
2006	Minimal March Tests for Dynamic Faults in Random Access Memories abstract The class of dynamic faults has been recently shown to be an important class of faults for the new technologies of random access memories (RAM) with significant impact on DPM levels. Very little research has been done in the design of memory test algorithms targeting dynamic faults. Two March test algorithms of complexity 11N and 22N, N is the number of memory cells, for subclasses of two-operation single-cell and two-cell dynamic faults respectively were proposed earlier by other authors. Also a March test of complexity 100N was proposed by them for detection of two-cell dynamic faults with two fault-sensitizing operations both applied on the victim or aggressor cells. In this paper, for the first time, minimal March test algorithms are proposed for two-operation single-cell and two-cell dynamic faults. The previously known March test algorithm for detection of two-operation two-cell dynamic faults is improved by 30N Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	ETS	1
2006	Minimal March Test Algorithm for Detection of Linked Static Faults in Random Access Memories abstract In this paper, a new notion of 2-composite static faults covering all unlinked and (realistic) linked static faults is introduced. We have introduced 120 new linked fault primitives missing in the paper by Hamdioui et al (IEEE TCAD 2004), thus extending the universe of linked fault primitives known before by 25%. A march test algorithm of length 23N (N - number of memory words) for detection of linked static faults in random access memories is proposed. It reduces the length of a previously known algorithm (Hamdioui et al., IEEE TCAD 2004) by 18N. We proved the proposed test is of minimum length Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	VTS	1
2005	Minimal March Tests for Unlinked Static Faults in Random Access Memories abstract New minimal March test algorithms are proposed for detection of (all) unlinked static faults in random access memories. In particular, a new minimal March MSS test of complexity I8N is introduced detecting all realistic simple static faults, as March SS (22N), (S. Hamdioui, van de Goor, Rodgers, MTDT 2002). Gurgen Harutunyan, Valery A. Vardanian, Yervant Zorian	VTS	1