This paper proposes structures of multi-path filters robust to substrate noise and nonlinearity of elements under low supply voltage to achieve wide dynamic range. They are derived by combining two structures which have been known to suppress substrate noise and nonlinearity more than the balanced one. Dynamic ranges and substrate noises of three proposed structures, the balanced (two-path) one, and the single ended (one-path) one are examined and simulation results show that the proposed structures reduce substrate noise and nonlinearity more than the conventional structures.

This paper discusses the input range limitation problems in track-and-hold circuit and the compensation method using a bootstrapped switch. A bootstrapped switch with an additional control circuit is proposed to compensate charge loss in conventional bootstrapped switch circuit. Simulation results using 0.18μm CMOS process parameters show that the proposed circuit reduces the bootstrap capacitance down to 25% for the conventional circuit.

This paper proposes a low-power, small chip area design technique for flash analog-to-digital converters (A/D converters). The proposed technique reduces power consumption of flash A/D converters by 50 % reduction of the number of comparators. Because output signals of flash A/D converters are thermometer code, only a few comparators whose reference voltages are around the input signal are significant and the other comparators can be removed. A novel track and hold circuit (T/H circuit) which can exchange its two balanced output signals is introduced. Thanks to the T/H circuit, the required input range of the comparator is limited to half of that of conventional one. The proposed A/D converter using the proposed T/H circuit can realize the same accuracy with the conventional one. The proposed technique is applied to a 6-bit 528 Msamples/s A/D converter realization. Its power consumption is evaluated by HSPICE simulations. It is confirmed that the proposed technique can save 34% of power consumption compared with conventional one.

In this paper, the matched performance of a dual band PIFA antenna is reported. The transducer power gain of the matched antenna is optimized over the popular commercial wireless communication bands of 824-960 MHz and 1710-1990 MHz using only one matching network. The antenna matching network was designed using the simplified real frequency technique and it was realized employing 0.18μm Si-processing technology. It is exhibited that realized matching network can be used for mass production for commercial use in multi band wireless communication systems.

A new architecture for class A CMOS current conveyor is proposed. The proposed circuit is free from the body effect and provides high performance in terms of input resistance and transfer gain errors. HSPICE simulation using 2 /spl mu/m process parameters also confirms the effectiveness of the proposed circuit.

An operational transconductance amplifier (OTA) is one of the most important analog building blocks. This paper proposes a novel voltage-regulating circuit for an OTA realization. The voltage-regulating circuit allows one to implement a simple structure OTA using MOSFET's in the non-saturation region. The resultant OTA using the proposed voltage-regulating circuit operates under a single 1.5 V power supply voltage. Simulation results of the OTA show harmonic distortion less than 1% even when 0.7 V/sub p-p/ input voltage is applied. Its power consumption is 85.8 /spl mu/W and cutoff frequency is 7 MHz.

Class AB differential amplifiers are proposed. Class AB operation for differential amplifiers is realized by using a minimum voltage selecting circuit and an amplifier. An almost minimum tail current value is provided to a differential amplifier to reduce extra power dissipation. The simulation results show that the static power consumption of Wang's OTA [1990] using the proposed method can be reduced from 244 /spl mu/W to 46 /spl mu/W.

This paper presents a method to minimize the finite wordlength error in output signals of linear phase 2-D FIR filters. The finite wordlength errors can be easily analyzed in the frequency domain when the input signal statistics are known. In the case of white input signals, impulse responses corresponding to all levels of input impulses are optimized so as to minimize the errors. A new ROM based filter structure is proposed in which the optimized impulse responses are stored in the ROM. The output signals are generated by superposing the impulse responses corresponding to the input levels. Many results of simulations confirm that the output signals of the proposed filters have far less errors than those of conventional filters.

The ATM transport network operation system described follows the TMN concept and supports CMIS/P interfaces to connect its subsystems. It contains about a hundred GDMO object classes, which were specially designed to achieve the operation system function. New technologies introduced to ensure effective and rapid system implementation include a directory system, to solve the problem of object instance location, and the use of GDMO object classes to design all system functions. In addition, an original common software platform is used to support the GDMO object intercommunication function. This operation system achieves a distributed object processing environment that supports CMIS/P interfaces. The system has been deployed in Japan and is now being used in multimedia experiments, the initial results of which are encouraging.

No abstract available.

This paper proposes an algorithm for the iterative design of FIR digital filters whose coefficients have minimum weight representation. The total number of nonzero bits is limited. In each iteration the coefficient vector is up-dated so that some sets of the amplitude ripples become smaller. The direction is found by solving linear simultaneous equations. The method evaluates the normalized peak ripples in the minimax sense. Several examples show that the proposed method yields superior filter responses compared to the conventional methods.

This paper introduces three highly linear single-capacitor MOSFET-C integrators for use in continuous-time filters. Only one capacitor per integrator is required to achieve complete cancellation of MOS nonlinearities. A fifth order lowpass Chebychev filter based on the design of the new integrators has been fabricated using a 2 micron CMOS process. The design procedures and experimental results from the fabricated chip are presented.>

The general principles of nonlinearity cancellation in MOS systems with MRC circuits are presented. The application of this technique is investigated for MOST-only digital-analog converter implementation.>

The generalized Neville algorithm is used to realize 3-band maximally flat linear phase FIR systems including bandstop and bandpass filters. A structure consisting of three subfilters each of which is a rectangular array of identical modules is derived. Bandstop and bandpass filters can be realized with two subfilters by appropriate ordering of the subfilters.>

A rearrangement-type digital cross-connect system (DCS) control algorithm is discussed. First, a time-space-time (TST) switch applicable to DCSs and a typical rearrangement algorithm are introduced, and the conditions for realizing a nondisturbing rearrangement are summarized. Next, a switch capability evaluation method is proposed and the effect of using this evaluation method to select a switch timeslot for accommodating a connection is shown. By analyzing general DCS control algorithms, a prearrangement technique is also developed that decreases blocking in a large-scale DCS control.>