Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern in VDSM technologies. It provides information about the SRAM design reliability, and its effectiveness is therefore mandatory for safety applications. Existing core-cell stability design-for-test (DfT) techniques consist in controlling the voltage levels of bit lines to apply a weak write stress on the core-cell under test. If the core-cell is weak, the weak write stress induces the faulty swap of the core-cell. However, these solutions are costly in terms of area and test application time, and generally require modifications of critical parts of the SRAM (core-cell array and/or the structure generating the internal auto-timing). In this paper, we present a new DfT technique for stability fault detection. It consists in modulating the word line activation in order to perform an adjustable weak write stress on the targeted core-cell for stability fault detection. Compared to existing DfT solutions, the proposed technique offers many advantages: programmability, low area overhead, low test application time. Moreover, it does not require any modification of critical parts of the SRAM.

In this paper, we present an exhaustive analysis of resistive- open defects in sense amplifiers of static random access memory designed with a 65 nm technology. We show that some resistive-open defects may lead to a new type of dynamic behavior that has never been experienced in the past. It is modeled by dynamic two-cell incorrect read faults of two different types. Such fault models represent failures in the sense amplifier, which prevent it from performing any read operations (in case of type 1 [1]) or only a single type of read operation (in case of type 2). Results of electrical simulations are presented to provide a complete understanding of such a faulty behavior and possible March test solutions are proposed to detect all d2cIRFs.

Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information of fault localization. However, these solutions are most of the time unable to distinguish between all faults, and more importantly often fail to identify the actual faulty block of the memory. Identifying which block of a memory (core- cell array, write drivers, address decoders, pre-charge circuits, etc ...) is defective allows saving considerable amount of time during the ramp up phase. In this paper, we propose a very low cost design-for-diagnosis (DfD) solution for identifying faulty write drivers. It consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver. The proposed solution allows a fast diagnosis (only three consecutive write operations are needed to fully diagnose the write driver) and induces a low area overhead (about 0.5% for a 512 times 512 SRAM). Beside diagnosis, an additional interest of such a solution is its usefulness during a post-silicon characterization process, where it can be used to extract the main features of write drivers (logic and analog levels on bit lines).

The usual techniques for memory diagnosis are mainly based on signature analysis. They consist in creating a fault dictionary that is used to determine the correspondence between the signature and the fault models affecting the memory. The effectiveness of such diagnosis methods is therefore strictly related to the fault dictionary accuracy. To the best of our knowledge, most of existing signature-based diagnosis approaches targets static faults only. In this paper, we present a new diagnosis approach that represents an alternative to signature-based approaches. This new diagnosis technique, named history-based diagnosis, makes use of the effect-cause paradigm already developed for logic design diagnosis. It consists in creating a database containing the history of operations (read and write) performed on a faulty memory core-cell. This information is crucial to track the root cause of the observed faulty behavior and it can be used to generate the set of possible fault primitives representing the set of suspected fault models. This new diagnosis method is able to identify static as well as dynamic faults. Although applied to SRAMs in this paper, it can be effective also for other memory types such as DRAMs. Experimental results are provided to prove the efficiency of the proposed methodology in generating a list of suspected faults as well as the location of the faulty components in the memory.

Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information on fault localization. However, these solutions are most of the time unable to distinguish between all faults, and more importantly often fail to identify the actual faulty block of the memory. Identifying which block of a memory (core- cell array, write drivers, address decoders, pre-charge circuits, etc ...) is defective allows to saving considerable amount of time during the ramp up phase. In this paper, we propose a very low cost design-for- diagnosis (DfD) solution for identifying faulty write drivers. It consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver. The proposed solution allows a fast diagnosis (only three consecutive write operations are needed to fully diagnose the write driver) and induces a low area overhead (about 0.5% for a 512 times 512 SRAM). Beside diagnosis, an additional interest of such a solution is its usefulness during a post-silicon characterization process, where it can be used to extract the main features of the write drivers (logic and analog levels on bit lines).

Nanoscaled SRAMs are now becoming more and more prone to device parameter deviations. In this paper, we consider threshold voltage (Vt) deviations in 6T core-cells designed with 90 nm technology. Static faults (transition and read destructive) but also dynamic faults (dynamic read destructive) are obtained as resulting faulty behaviors. Moreover, electrical data show that PVT (process, voltage, temperature) corners that maximize the detection of these faults are quite unconventional. Especially, we show that Vt deviations have their main impact at low voltage while hard defects, such as resistive-open defects in the core-cell, better manifest themselves at high voltage. This study of parameter deviations opens an additional problematic for the test of nanoscaled SRAMS that will be much more severe in deeper technologies (65 nm and 45 nm).

This paper presents an analysis of the electrical origins of slow write driver faults (SWDFs) (van de Goor et al., 2004) that may affect SRAM write drivers in 65nm technology. This type of fault is the consequence of resistive-open defects in the control part of the write driver. It involves an erroneous write operation when the same write driver performs two successive write operations with opposite data values. In the first part of the paper, we present the SWDF electrical phenomena and their consequences on the SRAM functioning. Next, we show how SWDFs can be sensitized and observed and how a standard March test is able to detect this type of fault

In this paper, we present an analysis of resistive-open defects in the sense amplifier of SRAMs designed with the Infineon 65 nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been published in the past. This faulty behavior can be modeled as a dynamic two-cell Incorrect Read Fault (d2cIRF). Such d2cIRF is the consequence of a failure in the sense amplifier which prevents it to perform any read operations. We show that it requires a specific sequence of read operations to be detected. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior. Finally, a possible March test solution is presented to allow the detection of d2cIRFs in all sense amplifiers of an SRAM.

In this paper, we present an analysis of resistive-open defects in the write driver of SRAMs designed with the Infineon 65nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been experienced in the past. This faulty behavior can be modeled as an un-restored destructive write fault (URDWF). Such URDWF is a consequence of the structural dependencies that exist between the write driver and the sense amplifier, and appears when a specific read operation is performed immediately after a specific write operation. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior and to highlight the difference with a standard un-restored write fault (URWF) model. Next, a possible March test solution is presented to detect URDWF. Finally, a discussion is proposed on the opportunity to include new features in this part of the memory to easily distinguish between faults coming from the write driver (like URDWF) and those coming from other parts of the memory (sense amplifier, core-cells, etc.)

Resistive-open defects appear more and more frequently in VDSM technologies. In this paper we present a study concerning resistive-open defects in the core-cell of SRAM memories. The first target of this work is a comparison of the effect produced by resistive-open defects in the 0.13 μm and 90 nm core-cell. We show that the 90 nm core-cell is more robust than the 0.13 μm core-cell in presence of resistive-open defects. On the other hand we show that dynamic faults are most likely to occur in the 90 nm than in 0.13 μm core-cell. Finally we propose a unique March test solution that ensures the complete coverage of all the extracted fault models for both technologies.

In this paper, we present an exhaustive study on the effects of resistive-open defects in the pre-charge circuits of SRAM memories. In particular, we have analyzed the influence of resistive-opens placed in different locations of these circuits. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled with un-restored write faults (URWFs) and un-restored read faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more rentable in terms of resistive defect detection than that of URRFs.

In this paper, we present a novel study on data retention faults (DRFs) in SRAM memories. We analyze in detail the electrical origins of these faults, starting from the most common till those that lead to what we have called hard to detect DRFs. In general, DRFs are supposed to be produced by very high resistive-open defects that affect the refreshment loop of the core-cell. We demonstrate that lower values of resistance may produce hard to detect DRFs. Moreover, each resistive-open defect produces a particular faulty behavior of the core-cell that changes for different ranges of the resistive value. We analyze different cases and we propose for each one an efficient test procedure based on March tests. In particular, we propose to stimulate the defective cells in some cases by indirect accesses and in some other cases by emphasizing natural noise phenomenon of SRAM memories (such as the ground bounce).

In this paper we present an exhaustive analysis of resistive-open defect in core-cell of SRAM memories. These defects that appear more frequently in VDSM technologies induce a modification of the timing within the memory (delay faults). Among the faults induce by such resistive-open defects there are static and dynamic read destructive fault (RDF), deceptive read destructive fault (DRDF), incorrect read fault (IRF) and transition fault (TF). Each of them requires specific test conditions and different kind of March tests are needed to cover all these faults (TF, RDF, DRDF and IRF). In this paper, we show that a unique March test solution can ensure the complete coverage of all the faults induced by the resistive-open defects in the SRAM core-cells. This solution simplifies considerably the problem of delay fault testing in this part of SRAM memories.

This paper presents an analysis of dynamic faults in core-cell of SRAM memories. These faults are the consequence of resistive-open defects that appear more frequently in VDSM technologies. In particular, the study concentrates on those defects that generate dynamic Read Destructive Faults, dRDFs. In this paper, we demonstrate that read or write operations on a cell involve a stress on the other cells of the same word line. This stress, called Read Equivalent Stress (RES), has the same effect than a read operation. On this basis, we propose to modify the well known March C-, which does not detect dRDFs, into a new version able to detect them. This is obtained by changing its addressing order with the purpose of producing the maximal number of RES. This modification does not change the complexity of the algorithm and its capability to detect the former target faults.