Summary form only given. We present a new AnalogRouter, specifically developed to address the problems of current densities and electromigration in the routing of multi-terminal, non-planar signal nets in analog circuits. The contributions of our work are: a new current characterization method based on current vectors attached to each terminal; current-driven Steiner tree generation which effectively determines all branch currents prior to detailed routing; and a run-time and memory efficient detailed routing strategy which addresses all features of current-driven circuits, particularly varying wire widths.

We present a new methodology for current driven routing and layout verification for analog applications used to avoid defects due to electromigration.

We present the single layer router CDR (Current Driven Router) capable of routing analog multiterminal signal nets with current driven wire widths. The widths used during routing are determined by current properties per terminal gained by simulation or manually specified by circuit designers. The algorithm presented computes a Steiner tree layout satisfying all specified current constraints while obeying the maximum allowed current densities on all connections. CDR calculates the Steiner tree topology, computes the unknown currents of wires connecting two Steiner points and generates the final Steiner tree layout in a single step thus eliminating the need for a separate layout post-processing step common to power and ground routing algorithms. CDR uses a connection graph for layout representation and applies an advanced minimum detour algorithm in combination with a modified 'three-point steinerization' heuristic for Steiner tree based layout construction.