Yonsang Cho

dblp:07/4467 · DBLP profile ↗
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3ranked-venue papers
1as first author
2since 2021 · last 2026
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author · 2 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 4 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.112005
On reducing test application time for scan circuits using limited scan operations and transfer sequences · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Electronic design automation › hardware verification and test › design for testability
scan-based testing
0.112005
On reducing test application time for scan circuits using limited scan operations and transfer sequences · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Electronic design automation › hardware verification and test
test application time reduction
0.112005
On reducing test application time for scan circuits using limited scan operations and transfer sequences · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005
Electronic design automation › hardware verification and test
test compaction
0.112005
On reducing test application time for scan circuits using limited scan operations and transfer sequences · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2005

Methods — techniques the papers use, named apart from their topics

transfer sequence · 0.1scan chain compaction · 0.1
YearPublicationVenuePosition
2026 Late Breaking Results - Test Selection for In-Field Testing Using a Two-Dimensional Aging Space
Irith Pomeranz, Subashini Gopalsamy, Arani Sinha, Yonsang Cho
VTS4
2022 Multi-die Parallel Test Fabric for Scalability and Pattern Reusability
abstract
With increase in functionality expected of a chip, it is becoming increasingly difficult to contain the entire logic in a single die. This is because higher die area leads to lower yield, and therefore to improve yield, die disaggregation is gradually becoming a standard practice across the industry. Additionally, not all functionality requires a leading-edge process technology, so different functionality can be partitioned across heterogenous dies. This has led to packages with multiple heterogenous dies. In this work, we describe a test fabric that is scalable across multiple dies. First, we describe different components of a scalable test fabric architecture. Second, we describe how pattern sets for a die can be re-used in different package configurations of which the die is a component. Third, we describe test generation methodology for disaggregated dies with identical logic blocks.
Arani Sinha, Yonsang Cho, Jon Easter, Meizel V. Leiva Rojas
ITC2
2005 On reducing test application time for scan circuits using limited scan operations and transfer sequences
abstract
The test application time of a scan circuit is a significant factor in the overall test cost of the circuit. Therefore, reducing the test application time is an important problem. The test application time of a test set for a scan circuit is determined by the sum of the number of scan shifts required for applying the test set and the number of primary input vectors in the test set. Compaction procedures that view a full-scan circuit as a combinational circuit reduce the number of test vectors, where a test vector consists of a scan vector and a primary input vector. However, this is not sufficient, and effective procedures must reduce the number of scan operations further than the combinational circuit view allows. Procedures to reduce the test application time by dropping scan operations and applying several primary input vectors between scan operations have been proposed earlier. The compaction procedures proposed in this work reduce the test application time further by using limited scan operations. Under a limited scan operation, the number of shifts is smaller than the length of a scan chain. Scan operations that cannot be dropped are replaced by limited scan operations under the proposed procedures.
Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1