VLDB 2026 Research / reviewers in the wild / expert
C. V. Ravi
dblp:07/5477
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 1977
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Memory systems · 68% Electronic design automation · 14% Distributed systems · 12% |
Topics — the 4 heaviest of 7, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory architecture
interleaved memory |
0.0 | 1 | 1972 | On the Bandwidth and Interference in Interleaved Memory Systems · IEEE Trans. Computers 1972 |
Memory systems › memory bandwidth
memory bandwidth modeling |
0.0 | 1 | 1972 | On the Bandwidth and Interference in Interleaved Memory Systems · IEEE Trans. Computers 1972 |
Memory systems
memory interference |
0.0 | 1 | 1972 | On the Bandwidth and Interference in Interleaved Memory Systems · IEEE Trans. Computers 1972 |
Performance modeling and evaluation
queueing models |
0.0 | 1 | 1972 | On the Bandwidth and Interference in Interleaved Memory Systems · IEEE Trans. Computers 1972 |
Methods — techniques the papers use, named apart from their topics
queueing model · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1977 | A Hierarchical Microcomputer System for Hardware and Software Development
C. V. Ravi, Torben Moller |
ISCA | 1 |
| 1976 | The Structure and Characteristics of Distributed Systems
C. V. Ravi |
ICSE | 1 |
| 1972 | On the Bandwidth and Interference in Interleaved Memory SystemsabstractA model to estimate the bandwidth and interference in an interleaved memory system in a multiprocessor system is described. The model allows queuing on busy modules, and the results obtained show that previous results are rather pessimistic. C. V. Ravi |
IEEE Trans. Computers | 1 |