Abstract The exponential growth of unstructured documents generated daily underscores the urgent need to develop technologies to structure information effectively. Traditional Information Extraction (IE) models enable the transformation of textual data into structured formats (e.g., semantic triplets), facilitating efficient searches and uncovering hidden data insights. However, they require predefined ontologies and, often, extensive human efforts. On the other hand, Open IE tools extract information without any input knowledge, but they are limited in capturing entire and in-depth contexts. Furthermore, the state of the art presents a substantial discrepancy between the efforts carried out in English-centric methods and those in low-resource languages, such as Italian. Our study aims to address the aforementioned key challenges. To this end, we first define Open Named Information Extraction (ONIE), an approach that generalizes IE across diverse domains without requiring input ontologies and captures complex relationships. Then, we develop LLIMONIIE (Large Language Instructed Model for Open Named Italian Information Extraction), a novel end-to-end generative information extraction framework that leverages the capabilities of Large Language Models (LLMs) to perform ONIE from Italian documents, able to extract Named Entities and Open Relations uniformly. Furthermore, we devise an innovative dataset generation methodology to support our research. Finally, we release the code and dataset, contributing to the scientific community and the development of low-resource languages. Experiments demonstrate the potential of our proposal, achieving competitive results compared to the actual state of the art of Italian IE.

In the recent digitization era, capturing, representing, and understanding knowledge is essential in countless real-world scenarios. Knowledge graphs emerged as a powerful tool for representing information through an adequately interconnected and interpretable structure in such a context. Nevertheless, generating proper knowledge graphs usually requires significant manual effort and domain expertise, resulting in graphs often affected by human subjectivity, limited scalability, or inability to capture implicit knowledge or handle heterogeneity. This paper proposes an innovative zero-shot strategy tailored to uncover reliable knowledge from text leveraging the recent highly effective generative large language models, with a particular focus on the GPT-3.5 model. Our proposal aims to create a suitable knowledge graph or improve existing ones by discovering missing qualitative triples. To assess the effectiveness of our methodology, we performed experiments on domain-specific datasets, confirming its potential for scalable and versatile knowledge discovery.

Efficiently verifying the customer’s identity is essential for ensuring the security of online transactions. Such verification is mainly accomplished according to the widespread Know Your Client (KYC) protocol, which relies on a self-identification handled by the user, typically providing personal data from their identification document (ID). In the current digital communication generation, such a task is usually performed by uploading a digital copy of the document by scanning or taking a real-time picture from a personal device such as a smartphone or tablet. Such activity, which usually involves manual data entry, is time-consuming and prone to human errors. Document Understanding (DU) has emerged as a crucial factor for automating data extraction in this scenario. One of its main challenges is the scarcity of data, which is barely available for security and privacy concerns. To this end, this paper proposes a solution that takes advantage of recent advances in DU to devise an innovative strategy for Identity Document Recognition (IDR), i.e., the task aimed at automatically understanding, extracting, and transcribing the fields of an ID card. We devised a two-stage approach based on fine-tuning a pre-trained model on synthetic and real-world data. We also developed a dedicated synthetic data generation tool to support the IDR process. Experimental results demonstrated the effectiveness of our methodology.

Workplace safety is a prominent concern, motivating researchers across diverse disciplines to investigate valuable ways to address its challenges. However, creating an efficient system to address this issue remains a significant challenge. Since many accidents happen due to improper usage or complete removal of Personal Protective Equipment (PPE), one straightforward method for enhancing workplace security involves monitoring their usage This paper introduces an Operator Area Network (OAN) system which improves the existing solutions by increasing portability across different users and environments, non-intrusiveness and privacy. To enhance robustness in detecting the situations in which PPEs are not used correctly, we take advantage of Machine Learning to analyse the received signal strength indicator (RSSI) between PPEs in the same OAN The novelty of this work is that it does not exploit RSSI as a proxy of the distance but instead recognises a signature of the correct wearing of the PPE By employing this system, employers can effectively ensure the proper usage of PPE devices at their worksites while also minimising any adverse effects on workers’ comfort and reducing the setup burden for employers. The system runs a Support Vector Machine (SVM) model several times per second and employs a post-processing algorithm to enhance its initial accuracy further As a result, the system effectively reduces false positives by about 80% and swiftly detects instances of improper usage of the worker’s PPE, raising the alarm in less than seven seconds. Moreover, the post-processing algorithm can be customised to meet the specific needs of different use cases, allowing for a flexible trade-off between the detection time interval and the overall accuracy of the detection system.

Abstract Ultrasound is a readily available, non-invasive and low-cost screening for the identification of endometriosis lesions, but its diagnostic specificity strongly depends on the experience of the operator. For this reason, computer-aided diagnosis tools based on Artificial Intelligence techniques can provide significant help to the clinical staff, both in terms of workload reduction and in increasing the overall accuracy of this type of examination and its outcome. However, although these techniques are spreading rapidly in a variety of domains, their application to endometriosis is still very limited. To fill this gap, we propose and evaluate a novel multi-scale ensemble approach for the automatic segmentation of endometriosis lesions from transvaginal ultrasounds. The peculiarity of the method lies in its high discrimination capability, obtained by combining, in a fusion fashion, multiple Convolutional Neural Networks trained on data at different granularity. The experimental validation carried out shows that: (i) the proposed method allows to significantly improve the performance of the individual neural networks, even in the presence of a limited training set; (ii) with a Dice coefficient of 82%, it represents a valid solution to increase the diagnostic efficacy of the ultrasound examination against such a pathology.

This work is focused on the sailing domain, for which several innovative technologies are being adopted to improve sailing efficiency, performance, and safety. In this context a knowledge graph could be used, for example, to represent information about different types of boats, sailing techniques, maritime safety, or weather conditions. Although numerous construction methods or ready-to-go knowledge graphs have been proposed in many fields, the sailing domain still needs to be explored. As the most effective methods rely on domain-specific datasets, the absence of suitable and available sailing datasets is one of the main challenges. Although several Open Information Extraction (OpenIE) methods may generate relevant triplets (the elementary units composing a knowledge graph) from arbitrary text without any additional information about its topic, such methods usually generate many incorrect triplets. In this paper, we aim (i) to address the aforementioned problem by proposing an innovative method that combines in an improved and strengthened way different OpenIE tools to generate proper triplets from domain-specific sources and, in particular, (ii) to build and release a suitable dataset for the sailing domain. Results confirm that our proposal can maximize the extracted information and infer unique information irretrievable by the classical OpenIE tools and, furthermore, that the generated dataset is significantly valuable for the sailing scenario.

Abstract In the last years, scientific and industrial research has experienced a growing interest in acquiring large annotated data sets to train artificial intelligence algorithms for tackling problems in different domains. In this context, we have observed that even the market for football data has substantially grown. The analysis of football matches relies on the annotation of both individual players’ and team actions, as well as the athletic performance of players. Consequently, annotating football events at a fine-grained level is a very expensive and error-prone task. Most existing semi-automatic tools for football match annotation rely on cameras and computer vision. However, those tools fall short in capturing team dynamics and in extracting data of players who are not visible in the camera frame. To address these issues, in this manuscript we present FootApp, an AI-based system for football match annotation. First, our system relies on an advanced and mixed user interface that exploits both vocal and touch interaction. Second, the motor performance of players is captured and processed by applying machine learning algorithms to data collected from inertial sensors worn by players. Artificial intelligence techniques are then used to check the consistency of generated labels, including those regarding the physical activity of players, to automatically recognize annotation errors. Notably, we implemented a full prototype of the proposed system, performing experiments to show its effectiveness in a real-world adoption scenario.

The rating of users requesting financial services is a growing task, especially in this historical period of the COVID-19 pandemic characterized by a dramatic increase in online activities, mainly related to e-commerce. This kind of assessment is a task manually performed in the past that today needs to be carried out by automatic credit scoring systems, due to the enormous number of requests to process. It follows that such systems play a crucial role for financial operators, as their effectiveness is directly related to gains and losses of money. Despite the huge investments in terms of financial and human resources devoted to the development of such systems, the state-of-the-art solutions are transversally affected by some well-known problems that make the development of credit scoring systems a challenging task, mainly related to the unbalance and heterogeneity of the involved data, problems to which it adds the scarcity of public datasets. The Region-based Training Data Segmentation (RTDS) strategy proposed in this work revolves around a divide-and-conquer approach, where the user classification depends on the results of several sub-classifications. In more detail, the training data is divided into regions that bound different users and features, which are used to train several classification models that will lead toward the final classification through a majority voting rule. Such a strategy relies on the consideration that the independent analysis of different users and features can lead to a more accurate classification than that offered by a single evaluation model trained on the entire dataset. The validation process carried out using three public real-world datasets with a different number of features. samples, and degree of data imbalance demonstrates the effectiveness of the proposed strategy. which outperforms the canonical training one in the context of all the datasets.

The relatively recent introduction on the market of low-cost devices able to perform an Electroencephalography (EEG) has opened a stimulating research scenario that involves a large number of researchers previously excluded due to the high costs of such hardware. In this regard, one of the most stimulating research fields is focused on the use of such devices in the context of biometric systems, where the EEG data are exploited for user identification purposes. Based on the current literature, which reports that many of these systems are designed by combining the EEG data with a series of external stimuli (Evoked Potentials) to improve the reliability and stability over time of the EEG patterns, this work is aimed to formalize a biometric identification system based on low-cost EEG devices and simple stimulation instruments, such as images and sounds generated by a computer. In other words, our objective is to design a low-cost EEG-based biometric approach exploitable on a large number of real-world scenarios.

Machine learning techniques have recently become the norm for detecting patterns in financial markets. However, relying solely on machine learning algorithms for decision-making can have negative consequences, especially in a critical domain such as the financial one. On the other hand, it is well-known that transforming data into actionable insights can pose a challenge even for seasoned practitioners, particularly in the financial world. Given these compelling reasons, this work proposes a machine learning approach powered by eXplainable Artificial Intelligence techniques integrated into a statistical arbitrage trading pipeline. Specifically, we propose three methods to discard irrelevant features for the prediction task. We evaluate the approaches on historical data of component stocks of the S&P500 index and aim at improving not only the prediction performance at the stock level but also overall at the stock set level. Our analysis shows that our trading strategies that include such feature selection methods improve the portfolio performances by providing predictive signals whose information content suffices and is less noisy than the one embedded in the whole feature set. By performing an in-depth risk-return analysis, we show that the proposed trading strategies powered by explainable AI outperform highly competitive trading strategies considered as baselines.

Abstract Offering timely support to users in eCoaching systems is a key factor to keep them engaged. However, coaches usually follow a lot of users, so it is hard for them to prioritize those with whom they should interact first. Timeliness is especially needed when health implications might be the consequence of a lack of support. In this paper, we focus on this last scenario, by considering an eCoaching platform for runners. Our goal is to provide a coach with a ranked list of users, according to the support they need. Moreover, we want to guarantee a fair exposure in the ranking, to make sure that users of different groups have equal opportunities to get supported. In order to do so, we first model their performance and running behavior and then present a ranking algorithm to recommend users to coaches, according to their performance in the last running session and the quality of the previous ones. We provide measures of fairness that allow us to assess the exposure of users of different groups in the ranking and propose a re-ranking algorithm to guarantee a fair exposure. Experiments on data coming from the previously mentioned platform for runners show the effectiveness of our approach on standard metrics for ranking quality assessment and its capability to provide a fair exposure to users. The source code and the preprocessed datasets are available at: https://github.com/wiguider/Fair-Performance-based-User-Recommendation-in-eCoaching-Systems .

Manual event tagging may be a very long and stressful activity, due the monotonous operations involved. This is particularly true when dealing with online video tagging, as for football matches, in which the burden of events to tag can consist of many thousands of actions, according to the desired level of granularity. In this work we describe an actual solution, developed for an existing football match tagging application, in which the GUI has been enhanced and integrated with a Voice User Interface, aiming at reducing tagging time and error rate. Empirical tests have revealed the efficiency and the benefits brought by the developed solution.

Given the overwhelming growth of online videos, providing suitable video thumbnails is important not only \nto influence user’s browsing and searching experience, but also for companies involved in exploiting video \nsharing portals (YouTube, in our work) for their business activities (e.g., advertising). A main requirement for \nautomated thumbnail generation frameworks is to be highly reliable and time-efficient, and, at the same time, \neconomic in terms of computational efforts. As conventional methods often fail to produce satisfying results, \nvideo thumbnail generation is a challenging research topic. In this paper, we propose two novel approaches \nable to provide relevant thumbnails with the minimum effort in terms of time execution and computational \nresources. The proposals rely on an object recognition framework which captures the most topic-related \nframes of a video, and selects the thumbnails from its resulting frames set. Our approach is a trade-off between \ncontent-coverage and time-efficiency. We perform preliminary experiments aimed at assessing and validating \nour models, and we compare them with a baseline compliant to the state-of-the-art. The assessments confirm \nour expectations, and encourage the future improvement of the proposed algorithms, as our proposals are \nsignificantly faster and more accurate than the baseline.

Nowadays, the prevention of credit card fraud represents a crucial task, since almost all the operators in the E-commerce environment accept payments made through credit cards, aware of that some of them could be fraudulent. The development of approaches able to face effectively this problem represents a hard challenge due to several problems. The most important among them are the heterogeneity and the imbalanced class distribution of data, problems that lead toward a reduction of the effectiveness of the most used techniques, making it difficult to define effective models able to evaluate the new transactions. This paper proposes a new strategy able to face the aforementioned problems based on a model defined by using the Discrete Fourier Transform conversion in order to exploit frequency patterns, instead of the canonical ones, in the evaluation process. Such approach presents some advantages, since it allows us to face the imbalanced class distribution and the cold-start issues by involving only the past legitimate transactions, reducing the data heterogeneity problem thanks to the frequency-domain-based data representation, which results less influenced by the data variation. A practical implementation of the proposed approach is given by presenting an algorithm able to classify a new transaction as reliable or unreliable on the basis of the aforementioned strategy.

The massive increase in financial transactions made in the e-commerce field has led to an equally massive increase in the risks related to fraudulent activities. It is a problem directly correlated with the use of credit cards, considering that almost all the operators that offer goods or services in the e-commerce space allow their customers to use them for making payments. The main disadvantage of these powerful methods of payment concerns the fact that they can be used not only by the legitimate users (cardholders) but also by fraudsters. Literature reports a considerable number of techniques designed to face this problem, although their effectiveness is jeopardized by a series of common problems, such as the imbalanced distribution and the heterogeneity of the involved data. The approach presented in this paper takes advantage of a novel evaluation criterion based on the analysis, in the frequency domain, of the spectral pattern of the data. Such strategy allows us to obtain a more stable model for representing information, with respect to the canonical ones, reducing both the problems of imbalance and heterogeneity of data. Experiments show that the performance of the proposed approach is comparable to that of its state-of-the-art competitor, although the model definition does not use any fraudulent previous case, adopting a proactive strategy able to contrast the cold-start issue.

The growth of the Web 2.0 has brought to a widespread use of social media systems. In particular, social bookmarking systems are a form of social media system that allows to tag bookmarks of interest for a user and to share them. The increasing popularity of these systems leads to an increasing number of active users and this implies that each user interacts with too many users ("social interaction overload"). In order to overcome this problem, we present a friend recommender system in the social bookmarking domain. Recommendations are produced by mining user behavior in a tagging system, analyzing the bookmarks tagged by a user and the frequency of each used tag. Experimental results highlight that, by analyzing both the tagging and bookmarking behavior of a user, our approach is able to mine preferences in a more accurate way, with respect to state-of-the-art approaches that consider only tags.

In the last years, researchers are experimenting with innovative methodologies to help people in their daily training routines. Our research activity focuses on the study of the effects of the former technologies on people's sport habits. This work describes an experimentation conducted on Everywhere Run! (EWRun), a mobile application part of a bigger platform, that aims at helping people to stay active behaving like a virtual personal trainer. In this work we show some interesting results that arise from recent radical changes we made to the software usability and its graphical design. We observed a considerable increment of the user base and, as a consequence, of the total number of daily trainings. To statistically prove the effectiveness of the redesign, we decided to compare the two versions of the application. The results confirm its effectiveness in terms of usability and brought us to investigate how the new design is affecting user motivation by means of a custom questionnaire and a well known motivation assessment tool. The positive result observed will be the starting point of our forthcoming researches: we aim at further validating the results presented in this work over a longer period of time and over a larger number of real users.

Runtime frequency and voltage adaptation has become very attractive for current and next generation embedded multicore platforms because it allows handling the workload variabilities arising in complex and dynamic utilization scenarios. The main challenge of dynamic frequency adaptation is to adjust the processing speed of each element to match the quality-of-service requirements in the presence of workload variations. In this paper, we present a control theoretic approach to dynamic voltage/frequency scaling for data-flow models of computations mapped to multiprocessor systems-on-chip architectures. We discuss, in particular, nonlinear control approaches to deal with general streaming applications containing both pipeline and parallel stages. Theoretical analysis and experiments, carried out by means of a cycle-accurate energy-aware multiprocessor simulation platform, are provided. We have applied the proposed control approach to realistic streaming applications such as Data Encryption Standard and software-based FM radio.

Die-temperature control to avoid hotspots is increasingly critical in multiprocessor systems-on-chip (MPSoCs) for stream computing. In this context, thermal balancing policies based on task migration are a promising approach to redistribute power dissipation and even out temperature gradients. Since stream computing applications require strict quality of service and timing constraints, the real-time performance impact of thermal balancing policies must be carefully evaluated. In this paper, we present the design of a lightweight thermal balancing policy MiGra, which bounds on-chip temperature gradients via task migration. The proposed policy exploits run-time temperature as well as workload information of streaming applications to define suitable run-time thermal migration patterns, which minimize the number of deadline misses. Furthermore, we have experimentally assessed the effectiveness of our thermal balancing policy using a complete field-programmable-gate-array-based emulation of an actual three-core MPSoC streaming platform coupled with a thermal simulator. Our results indicate that MiGra achieves significantly better thermal balancing than state-of-the-art thermal management solutions while keeping the number of migrations bounded.

As feature sizes decrease, power dissipation and heat generation density exponentially increase. Thus, temperature gradients in multiprocessor systems on chip (MPSoCs) can seriously impact system performance and reliability. Thermal balancing policies based on task migration have been proposed to modulate power distribution between processing cores to achieve temperature flattening. However, in the context of MPSoC for multimedia streaming computing, where timeliness is critical, the impact of migration on quality of service must be carefully analyzed. In this paper we present the design and implementation of a lightweight thermal balancing policy that reduces on-chip temperature gradients via task migration. This policy exploits run-time temperature and load information to balance the chip temperature. Moreover, we assess the effectiveness of the proposed policy for streaming computing architectures using a cycle-accurate thermal-aware emulation infrastructure. Our results using a real-life software defined radio multitask benchmark show that our policy achieves thermal balancing while keeping migration costs bounded.

Leakage power has an increasing relevance for recent and future embedded technologies. Moreover, its contribution is heavily dependent on runtime temperature and process variations, that strongly impact the effectiveness of energy management strategies. Furthermore, in the context of streaming embedded systems, aggressive shutdown techniques that are typically applied to reduce leakage contribution are not suitable because of their negative effect on throughput. In this work we propose a leakage-aware approach for streaming applications that: i) Exploits feedback control policy to guarantee throughput by observing output data rate; ii) Levarages runtime temperature information to adjust the control law so that leakage energy is minimized independently from process variations and temperature conditions. Results show how temperature and leakage variations impact energy management strategies and how the proposed approach is effective in reducing total power consumption.

Network on Chip architectures are proposed as a solution to overcome functional and physical scalability shown by shared bus based MPSoC architecture. Unfortunately to implement and efficient communication infrastructure, the designer has to set a lot of parameters. An exhaustive knowledge of how the chosen settings influence the overall behaviour of the designed system is then mandatory. Aim of this paper is to discuss the relationship between the performances of a NoC and its configuration parameters in the case of traffic generated by cache operations (block replacements). We paid special attention to investigate the impact of the serialization factor, that was already not clearly assessed in literature for this important case study. A numerical analysis, referring to an actual implementation of the NoC on a state-of-the-art 65 nm technological process was performed. The obtained results were used to report an energy and execution time exploration over the complete design space of interest.

Multi-Processor System-On-Chip (MPSoC) can provide the performance levels required by high-end embedded applications. However, they do so at the price of an increasing power density, which may lead to thermal runaway if coupled with low-cost packaging and cooling. Hence, mechanisms to efficiently evaluate the effectiveness of advanced thermal-aware operating-system (OS) strategies (e.g. task migration) onto the available MPSoC hardware are needed. In this paper, we propose a new MPSoC OS emulation framework that enables the study of thermal management strategies at the architectural- and OS-levels with the help of a standard FPGA. This framework includes the hardware and software components needed to accurately model complex MPSoCs architectures, and to test the effects of run-time thermal management strategies at the OS/middleware level with real-life inputs. Our results show that migration overhead is negligible w.r.t. temperature timings, enabling the development of thermal-aware migration strategies. Moreover, the effectiveness of the monitoring and feedback mechanism provides an emulation performance only ten times slower than real time.

The ever-shrinking lithographic technologies available to chip designers enable performance and functionality breakthroughs; yet, they bring new hard problems. For example, multiprocessor systems-on-chip featuring several processing elements can be conceived, but efficiently interconnecting them while keeping the design complexity manageable is a challenge. Traditional buses are easy to deploy, but cannot provide enough bandwidth for such complex systems. A departure from legacy architectures is therefore called for. One radical path is represented by packet-switching networks-on-chip, whereas a more conservative approach interleaves bandwidth-rich components (e.g., crossbars) within the preexisting fabrics. This paper is aimed at analyzing the strengths and weaknesses of these alternative approaches by performing a thorough analysis based on actual chip floorplans after the interconnection place&route stages and after a clock tree has been distributed across the layout. Performance, area, and power results will be discussed while keeping an eye on the scalability prospects in future technology nodes

In this work, we describe a control theoretic approach to dynamic voltage/frequency scaling (DVFS) in a pipelined MPSoC architecture with soft real-time constraints, aimed at minimizing energy consumption with throughput guarantees. Theoretical analysis and experiments carried out on a cycle-accurate, energy-aware, and multiprocessor simulation platform are provided. We give a dynamic model of the system behavior which allows to synthesize linear and nonlinear feedback control schemes for the run-time adjustment of the core frequencies. We study the characteristics of the proposed techniques in both transient and steady-state conditions. Finally, we compare the proposed feedback approaches and local DVFS policies from an energy consumption viewpoint.

Today, chip multiprocessors (CMPs) that accommodate multiple processor cores on the same chip have become a reality. As the communication complexity of such multicore systems is rapidly increasing, designing an interconnect architecture with predictable behavior is essential for proper system operation. In CMPs, general-purpose processor cores are used to run software tasks of different applications and the communication between the cores cannot be precharacterized. Designing an efficient network-on-chip (NoC)-based interconnect with predictable performance is thus a challenging task. In this paper, we address the important design issue of synthesizing the most power efficient NoC interconnect for CMPs, providing guaranteed optimum throughput and predictable performance for any application to be executed on the CMP. In our synthesis approach, we use accurate delay and power models for the network components (switches and links) that are obtained from layouts of the components using industry standard tools. The synthesis approach utilizes the floorplan knowledge of the NoC to detect timing violations on the NoC links early in the design cycle. This leads to a faster design cycle and quicker design convergence across the high-level synthesis approach and the physical implementation of the design. We validate the design flow predictability of our proposed approach by performing a layout of the NoC synthesized for a 25-core CMP. Our approach maintains the regular and predictable structure of the NoC and is applicable in practice to existing NoC architectures.

In this work we take a control-theoretic approach to feedback-based dynamic voltage scaling (DVS) in multi processor system on chip (MPSoC) pipelined architectures. We present and discuss a novel feedback approach based on both linear and non-linear techniques aimed at controlling interprocessor queue occupancy. Theoretical analysis and experiments, carried out on a cycle-accurate multiprocessor simulation platform, show that feedback-based control reduces energy consumption with respect to standard local DVS policies and highlight that non-linear strategies allows a more flexible and robust implementation in presence of variable workload conditions

Increasing miniaturization is posing multiple challenges to electronic designers. In the context of multi-processor system-on-chips (MPSoCs), we focus on the problem of implementing efficient interconnect systems for devices which are ever more densely packed with parallel computing cores. Easily seen that traditional buses can not provide enough bandwidth, a revolutionary path to scalability is provided by packet-switched network-on-chips (NoCs), while a more conservative approach dictates the addition of bandwidth-rich components (e.g. crossbars) within the preexisting fabrics. While both alternatives have already been explored, a thorough contrastive analysis is still missing. In this paper, we bring crossbar and NoC designs to the chip layout level in order to highlight the respective strengths and weaknesses in terms of performance, area and power, keeping an eye on future scalability

Reconfigurable FPGA/CPU systems are widely described in literature as a viable processing solution for embedded and high end processing. One of the key issues of this kind of approach is the code partitioning between CPU and FPGA. The development of automatic partitioning tools allows to obtain optimized architecture without a specific knowledge of digital design. In this paper we present a framework which, starting from an ANSI C application code: (i) automatically identifies code fragments suitable for hardware implementation as specialized functional units (ii) for all these segments a synthesizable code is generated and sent to a synthesis tool, (iii) from the synthesis results, the segments to be implemented on FPGA are selected (iv) bit stream to configure the FPGA and modified C code to be executed on the CPU are generated. We applied this tool to standard benchmarks obtaining, with respect to state of the art, an improvement of up to 250% in the accuracy of performances estimation related to the selected segments of code. This leads to a more optimized code partitioning

With increasing communication demands of processor and memory cores in Systems on Chips (SoCs), scalable Networks on Chips (NoCs) are needed to interconnect the cores. For the use of NoCs to be feasible in today's industrial designs, a custom-tailored, application-specific NoC that satisfies the design objectives and constraints of the targeted application domain is required. In this work, we present a design methodology that automates the synthesis of such application-specific NoC architectures. We present a floorplan aware design method that considers the wiring complexity of the NoC during the topology synthesis process. This leads to detecting timing violations on the NoC links early in the design cycle and to have accurate power estimations of the interconnect. We incorporate mechanisms to prevent deadlocks during routing, which is critical for proper operation of NoCs. We integrate the NoC synthesis method with an existing design flow, automating NoC synthesis, generation, simulation and physical design processes. We also present ways to ensure design convergence across the levels. Experiments on several SoC benchmarks are presented, which show that the synthesized topologies provide a large reduction in network power consumption (2.78x on average) and improvement in performance (1.59x on average) over the best mesh and mesh-based custom topologies. An actual layout of a multimedia SoC with the NoC designed using our methodology is presented, which shows that the designed NoC supports the required frequency of operation (close to 900 MHz) without any timing violations. We could design the NoC from input specifications to layout in 4 hours, a process that usually takes several weeks.

Networks on chip (NoC) has emerged as the paradigm for designing scalable communication architecture for systems on chips (SoCs). Avoiding the conditions that can lead to deadlocks in the network is critical for using NoCs in real designs. Methods that can lead to deadlock-free operation with minimum power and area overhead are important for designing application-specific NoCs. A major class of deadlocks that occur in NoCs are due to the dependencies among the resources shared by different message types. In this work, we consider the problem of avoiding message-dependent deadlocks during the NoC topology synthesis phase. We show that by considering this issue during topology synthesis, we can obtain a significantly better NoC design than traditional methods, where the deadlock avoidance issue is dealt with separately. Our experiments on several SoC benchmarks show that our proposed scheme provides large reduction in NoC power consumption (an average of 38.5%) and NoC area (an average of 30.7%) when compared to traditional approaches

The limited scalability of current bus topologies for systems on chips (SoCs) dictates the adoption of networks on chips (NoCs) as a scalable interconnection scheme. Current SoCs are highly heterogeneous in nature, denoting homogeneous, preconfigured NoCs as inefficient drop-in alternatives. While highly parametric, fully synthesizeable (soft) NoC building blocks appear as a good match for heterogeneous MPSoC architectures, the impact of instantiation-time flexibility on performance, power and silicon cost has not yet been quantified. The paper details /spl times/pipes Lite, a design flow for automatic generation of heterogeneous NoCs. /spl times/pipes Lite is based on highly customizable, high frequency and low latency NoC modules, that are fully synthesizeable. Synthesis results provide modules that are directly comparable, if not better, than the current published state-of-the-art NoCs in terms of area, power latency and target operating frequency measurements.