Physical unclonable functions (PUFs) are increasingly recognized as a key technology for enhancing hardware and the Internet of Things (IoT) security. The IoT devices are often plagued by weak security measures, making them susceptible to various external threats. To address these vulnerabilities, robust and reliable security solutions are critical. This study introduces a highly reliable and low-power PUF application-specific integrated circuit (ASIC) design specifically designed for the IoT security applications. Initially, the proposed design is deployed on a Xilinx ZYNQ 7000 field-programmable gate array (FPGA) board operating at 100 MHz and later designed and fabricated using the Cadence Innovus in the 180-nm CMOS process on silicon. This work presents and evaluates a novelxnor–xorring oscillator (RO) PUF with a configurable frequency. The design’s performance is analyzed using statistical metrics, including reliability, uniqueness, and uniformity. Thexnor–xorRO PUF ASIC demonstrates max reliability of 91.92%, a uniqueness of 49.62%, and a uniformity of 50.19% on silicon.

Most digital transformer designs used non-overlapping coil topology, which increases the design area on silicon. This study demonstrates a digital transformer based on a multi-layer, over-lapping coil topology that increases the trans-former’s mutual inductance. Two interwound coils composed of 6 metal layers are implemented to realize the transformer and fabricated using 18 µm HV CMOS process. To demonstrate the operation of the proposed transformer, the rise time (trise), fall time (tfall), and propagation delay (tpro_delay) of six chips are measured at an operating frequency of 10 MHz with a worst power consumption of 52 mW. The digital transformer is also tested at various duty cycles to ensure its suitability for power conversion applications.

This work presents a high-resolution programmable frequency divider to select the frequencies that will be generated in DCO (Digitally Controlled Oscillator) or VCO (Voltage Controlled Oscillator) that will benefit the design of high-speed, wide-range PLL for Internet-of-Things (IoT) applications. The design is verified through post-layout simulations at 1 GHz input clock. The design achieves a division ratio range of 2-2048 with minimum and maximum operating frequencies of 488 KHz and 500 MHz, respectively. This work is carried out using 40-nm CMOS technology at 60 pF capacitive load and an average power consumption in worst case post layout simulation is 0.470 mW at 500 MHz.

This paper presents a novel 6-Gbps variation insensitive input/output (I/O) buffer designed for DDR4 and DDR5 SDRAM data transfer in a 16-nm FinFET CMOS process. Utilizing genetic algorithm (GA) to model process, voltage, and temperature (PVT) variations, the study reveals insights into temperature and voltage effects on FinFET-based, nanoscale buffer characteristics, leading to the removal of the temperature detector circuit to save power and area. Voltage variations, however, significantly impact slew rate, prompting the introduction of a Voltage Detector circuit using ultra-low threshold voltage (ULVT) transistors. Innovative Voltage Level Converter, Pre-Driver, and Digital Logic Control circuits enhance slew rate and throughput while stabilizing the output signal quality. This results in reliable operation at 6.0 Gbps with improved slew rate (17.7%/39.75% for VDDIO =0.8/1.2 V) and duty cycle performance (50.5%/51.4% for VDDIO =0.8/1.2 V) due to PV auto-adjustment; the first in the world. The proposed design effectively addresses the stringent slew rate and data rate requirements of DDR4 and DDR5 SDRAMs, offering advancements in speed, reliability, and efficiency amidst PV variations.

Recent digital pulsewidth modulation (DPWM) researches use multiple clock inputs and long D flip-flop (DFF) arrays, which makes scaling to different DPWM frequencies challenging. This brief demonstrates a DPWM that utilizes a single clock and a Matrix shift array, allowing it to be scaled to any frequency and reducing the effects of clock skew. It has a clock gating technique that selects a specific row of DFFs based on the required % duty cycle. The DPWM design has a dead time generator to prevent shoot-throughs. The DPWM has been fabricated using UMC 180-nm CMOS process. The performance and functionality of the DPWM have been verified through the measured comparisons of % duty ratio, dead time ($T_{dt}$), and output frequency ($f_{\text {out}}$) at input clock frequency ($f_{\text {clk}_{\text {in}}}$) equal to 10$\sim $100 MHz. The DPWM design has a maximum % duty ratio of 90.6%,$T_{dt}$= 1.8 ns, and$f_{\text {out}}$= 6.25 MHz with 3.4-mW power consumption at$f_{\text {clk}_{\text {in}}}$= 100 MHz.

For high-resolution, high-accuracy applications, re-cent DPWM (digital PWM) researches use long DFF arrays, resulting in clock skew that may compromise DPWM performance. This study proposed a DPWM based on a matrix phase shifter and clock gating technique which only selects a specific row of DFFs during operation depending on the required level of$\mathrm{V}_{o}$. The proposed design minimizes the clock skew caused by redundant DFF array clock activity. In addition, it uses a single clock and does not need any extra signal for synchronization. It has a dead-time generator that prevents shoot-through. The proposed DPWM has been implemented in UMC 180-nm CMOS technology where an overall chip and core area of 1285 x 1285$\mu \mathbf{m}^{2}$and 725.1 x 282.8$\mu \mathbf{m}^{2}$are used, respectively. The all-PVT corner post-layout simulation confirmed the functionality of the design with a maximum duty cycle of 90.6% at$\mathbf{C}_{load}=60\ \text{pF}$and$\mathbf{f}_{clk}=100$MHz.

A time-difference amplifier (TDA) with a wide time-difference input range and variable gain is presented in this paper. Its time amplification is performed using novel current source architecture, phase detection, and variable delay circuits. After time amplification, to avoid the current sources for charging and discharging capacitors simultaneously, a reset circuit is added. To widen the input time-difference range, an adjustable current source control is added. The proposed TDA is implemented using TSMC 40-nm CMOS process. The core area is $209.42\times 84.775\mu \mathrm{m}^{2}$. Though our design is driven by a lower supply voltage, it has the widest time-difference input range and the largest FOM among all existing TDAs.

This investigation presents a digital logic accelerator (DLA) design of a neural network hardware that utilizes output reuse. The DLA is used in the detection mechanism of underwater objects that was deployed in an underwater vehicle. A modified YoloV3-tiny network was also implemented to detect more than 20 underwater objects. The proposed DLA uses processing units that have parallel architectures of output windows, and output channels. Moreover, a new Inter-Controller is designed to control the direct memory access (DMA) together with a new Reshape module to improve the performance and power efficiency. A detailed description of the design as well as the measurements on silicon are presented. The chip is realized using a typical 180-nm CMOS process. It showed a performance result of 40.96 GOPS and the power consumption is 196.8 mW. The DLA was tested to demonstrate 19.88 frames per second and 40.96 GOPS.

Underwater image processing has been shown to exhibit significant potential for exploring underwater environments. It has been applied to a wide variety of fields, such as underwater terrain scanning and autonomous underwater vehicles (AUVs)-driven applications, such as image-based underwater object detection. However, underwater images often suffer from degeneration due to attenuation, color distortion, and noise from artificial lighting sources as well as the effects of possibly low-end optical imaging devices. Thus, object detection performance would be degraded accordingly. To tackle this problem, in this article, a lightweight deep underwater object detection network is proposed. The key is to present a deep model for jointly learning color conversion and object detection for underwater images. The image color conversion module aims at transforming color images to the corresponding grayscale images to solve the problem of underwater color absorption to enhance the object detection performance with lower computational complexity. The presented experimental results with our implementation on the Raspberry pi platform have justified the effectiveness of the proposed lightweight jointly learning model for underwater object detection compared with the state-of-the-art approaches.

Double-edge triggered flip-flops (DETFF) project a solution to clock power reduction by lowering the clock frequency and maintains the same data rate. Hence, they are appropriate to be used as shift registers. This paper has reviewed several earlier designs of double-edge triggered flip-flops and presented an 8-bit low power shift register by using a newly designed DETFF. The major contribution of this work takes advantage of two parallel data paths that work in opposite phases of the single clock without an inverted input trigger. The proposed shift register design is realized using a typical 90-nm CMOS process. The post-layout results show that the proposed shift register reduces the power consumption by at least 17.2%.

This paper presents a computation in memory (CIM) architecture and circuit design featured with single command to execute addition, signed multiplication, and multi-function to resolve poor computation throughput caused by von Neumann bottleneck. The proposed CIM takes advantage of 2T-Switch circuit which needs only 2 switches to select the required computation units such that the area on silicon is reduced. RCAM (ripple carry adder and multiply) unit realized with full swing gate diffusion input (FS-GDI) in a single-ended disturb- free 7T SRAM further reduces the power consumption and active circuit area. Auto-switching write-back circuit consisting of BL auto-switching circuit, Data switching circuit, and WL auto-switching circuit facilitates the automatic restore of addition and multiplication to designated memory addresses. The proposed CIM is realized using 40-nm CMOS process to demonstrated 12.18/28.19 fJ/bit normalized write/read energy at 100 MHz system clock rate.

A very low energy -consuming SRAM design based on single-ended cells is demonstrated in this work. To resolve poor SNM (static noise margin) of prior single-ended memory cells, the porposed SRAM cell is equipped with a pull-up PMOS and a high-Vthn NMOS foot switch such that the cell state is not bothered by noise when the suppy voltage is getting lowered. Moreover, a PFOS (Positive Feedback Op-Amp Sensing) circuit is added between bitlines (BL, BL) to reduce the read delay and generate full-swing output. Last but not least, a voltage mode select (VMS) circuit is added to each column to reduce the static power of unselected cells such that idle power is drastically reduced. The reason is that the a lower voltage able to keep the state of bits is applied to those unselected cells. Not only are detailed description and all-PVT-corner simulations provided to predict the low power performance, a 1-kb SRAM design based on the proposed cells with BIST (build-in self test) circuit is realized using typical 40-nm CMOS technology. The worst energy/access and energy/bit are found to be 67.5 fJ, and 2.1 fJ, respectively.

This investigation proposes a computing-in-memory (CIM) design to circumvent the von Neumann bottleneck which causes limited computation throughput for effective artificial intelligence (AI) applications. The proposed CIM performs multiple operations such as single-instruction basic Boolean operations, addition, and signed number multiplication, and multiple functions such as normal mode and retention mode for the built-in self-test (BIST). Its 2T-Switch requires only two transistors to be utilized for static random-access memory (SRAM) array; thus, the arithmetic unit can be chosen easily and the area overhead is minimized. Its ripple carry adder and multiplier (RCAM) unit based on single-ended disturb-free 7T 1-Kb SRAM was developed using the full swing-gate diffusion input (FS-GDI) technology that has full voltage swing resolution, low power consumption, and less chip area cost. Its Auto-Switching Write Back Circuit restores addition and multiplication operations automatically to assigned memory address. The CIM is implemented using the TSMC 40-nm CMOS process, where the core area is$432.81 \times 510.265\,\,\mu \text{m}^{2}$. Among the related works, the proposed CIM performs the most number of operations and functions.

One of the most important functional units in digital circuitry for synchronization and measurement is time-to-digital converter (TDC) which always requires higher resolution and accuracy. In this brief, a process, voltage, temperature (PVT)-variation-insensitive TDC featured with a PVT detector is proposed. The PVT detector takes advantage of another delay line with optimized locking conditions to differentiate PVT corners. The proposed TDC is physically realized using a 90-nm CMOS process. On-silicon measurement results demonstrate 30-ps resolution, <; 1.5 LSB INL/DNL, and 2.22 mW at 100 MHz and 1.2-V supply voltage.

This paper presents a high efficiency buck converter with wide load current range. To improve the efficiency in wide load current range, the dual-mode of PWM and PSM is utilized. The proposed design is implemented with a typical 0.35 μm CMOS process. The peak efficiency is simulated to be 96.76% at load current of 1000 mA. Moreover, the efficiency is higher than 94.80% at the wide load current range from 10 mA to 1000 mA. Besides, the proposed design is switched smoothly between PWM and PSM by effective and reliable control logic circuit.

Traditional Li-ion battery chargers face a dilemma, which is the poor efficiency at a large charging current or vice versa. A pulse swallow technique is proposed in this investigation to resolve the mentioned problem. The proposed design carries out the automatic switching of PWM/PFM when the charging operation enters a light load scenario. When the battery voltage is close to the pre-defined full voltage, PFM strobes mask out the system clock to shut off power transistors to boost the efficiency. Post-layout simulations justify the proposed design generates 1.5 A current with 87.4%-88.6% efficiency.

In this brief, a four-stage pipeline read only memory (ROM)less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed. To attain higher spurious-free dynamic range (SFDR) and faster clock rate, the hardware cost and delay using different segments with various interpolation equations are analyzed systematically to explore the optimal solution. The second-order parabolic equations with proper coefficients and factorized operation orders based on optimized hardware cost and delay are finally utilized to enhance SFDR. The proposed design is demonstrated by the physical implementation using the TSMC 0.18-μm CMOS technology cell library and on-silicon measurements, where the maximum SFDR is 74 dBc, 0.018-mW/MHz power dissipation, and the maximal clock frequency is 71.9 MHz.

A primary-side output current estimator with process compensator for the flyback control circuits is designed and analyzed in this investigation. Flyback control circuits play a key role of smart lighting systems, where LED drivers require a compensator to keep the system stable. The process sensor is in charge of the detection of the chip process corner. Then, the process compensator correspondingly selects a comparator according to the output of the process sensor. Detailed analysis, including the method of the process sensor and the selection procedure of the process compensator, is reported. All-PVT-corner post-layout simulations of the proposed current estimator demonstrate 89.84 % efficiency, and 15.53 W power consumption given 5 V power supply and 50 kHz system clock rate.

This paper proposes a 40-nm CMOS 2×VDD buffer with slew rate (SR) variation compensated and dynamic leakage reduction during signal transitions. By using the dual variation detectors, five process corners for both nMOS and pMOS could be detected. Thus, the SR deviations will be significantly reduced by controlling the switches of the output stage accordingly. Besides, leakage reduction circuit will shut down current paths to reduce dynamic leakage after signal transitions are completed. This buffer design is implemented using the typical 40-nm CMOS process, where the active area is 0.052 × 0.213 mm2. The measured worst case of SR variation improvement is 20.8% and 54.9% when VDDIO is 0.9 and 1.8 V, respectively. The peak dynamic leakage is reduced to 41.0% and 37.5% at 0.9 and 1.8 V, respectively.

A 2×VDD I/O buffer with process and voltage (PV) compensation technique is proposed. In this research, the purpose of slew-rate compensation is to maintain slew rate (SR) within predefined ranges regardless PV variations. The reason of temperature variation is not considered is that it is found to be a relatively low correlation factor to slew rate for 90 nm process. All bias voltages in process and voltage variation detectors are generated from bandgap circuits such that variations have been guaranteed by simulation within less than 3.57%. Notably, we add a resistor in series of MOS gate to trace leakage current of wide transistors with a -0.1 (V/ns) on SR for trade off. The data rate is 800/500 MHz given 1.0/2.0 V supply voltage with 20 pF load, respectively, by all-corner simulations. The Δ SR improvement is 33.9% and 29.8% in the rising time, and 29.1% and 24.8% in the falling time of 1× VDD and 2× VDD, respectively. The core area is 0.052× 0.388 mm2.

This paper introduces a phase shift detector (PSD) with high accuracy for sensing applications. The proposed design comprises a Narrow bandpass filter, a Comparator, and an Offset calibration circuit. Narrow bandpass filter rejects all the signals except that generated from a Fixed-frequency Generator. To reduce the error caused by circuit noise and external interface, Offset calibration circuit (OCC) is utilized to calibrate the Comparator. The proposed phase shift detector circuit is realized on silicon using a 0.18 μm CMOS technology. The post-layout simulation results show that the proposed design is able to detect the phase difference from -90° to 90°, where the maximum output error of the proposed PSD is 2.37%. Besides, the power consumption is 4.365 mW @ 10 MHz given a 0.9 V power supply voltage.

A leakage current compensation design for nanoscale SRAMs is proposed in this paper. The proposed compensation design is composed of a leakage current sensor, which generates a warning signal if the leakage is over a predefined threshold, and a compensation circuit following the sensor, which will be activated to speed up the read operation. At 0.6 V system voltage, the proposed compensation design reduces 27.86% of the average power dissipation, and 54.88% of the read delay at the expense of 3.64% area overhead. The proposed Static Random-Access Memory is implemented using the TSMC 40-nm CMOS logic technology. The energy per access is measured to be 0.9411 pJ given a 600-mV power supply and a 54-MHz system clock rate.

This paper presents a voltage monitoring IC with high-voltage multiplexer (HVMUX) and HV transceiver for battery interconnect module (BIM) used in battery management systems (BMSs). The voltage monitoring IC must be able to accommodate input voltage up to tens of volts, perhaps even hundreds of volts, which is difficult to be realized using a logic-based solution. To realize a solution on silicon, the voltage monitoring IC shall be fabricated using an advanced HV semiconductor process, which usually is constrained by the voltage drop limitation between gate and source of HV devices. To overcome such a limitation, an HV switch is proposed in this paper, including an HV gate voltage driver (HVGVD) driving the HV MOS without any over-voltage hazard. In addition, an HV transceiver is proposed using CMOS transistors without any isolator. An experimental prototype is fabricated using a typical 0.25 μm 1-poly 3-metal 60 V BCD process. The measurement results reveal that the error and off-isolation of HVMUX is less than 2.54% and -92 dB@1 MHz, respectively. Meanwhile, the HV transceiver can transmit and receive data with a -32 ~ +32 V common voltage.

In this study, a 4+1 Kb static random-access memory (SRAM) with leakage sensor and read delay compensation is demonstrated, where single-ended 5T loadless SRAM cells are used. The energy per access is found to be 0.27 pJ provided that the SRAM fabricated by a typical 40 nm CMOS technology is powered by a 0.6 V supply. The leakage sensor and compensation circuits are carried out by dummy SRAM cells to mimic the leakage currents therein. The average power and read delay reduction of the proposed SRAM are 27.86% and 29.46%, respectively, based on all-PT-corner post-layout simulations.

This paper presents a temperature sensor with process compensation and second-order calibration for Battery Management Systems (BMS). Particularly, the second-order calibrated CTAT and PTAT sensors utilizing a current mirror and an n-well resistor are used to eliminate the second-order term of the temperature coefficient such that the relationship between the output voltage and the temperature is linearized. The proposed temperature sensor is implemented using a typical 0.18 μm CMOS process. The core area and power of the proposed temperature sensor are 0.177 mm2and 2.0 mW, respectively. In the range from -40°C to 125°C, the worst deviation of the temperature sensor is -1.49°C ~ +2.13°C at FF, TT, and SS corners, respectively. The maximum non-linearity reduction of second-order calibrated CTAT and PTAT sensors are 72.5% and 90.5%, respectively.

A high-speed compensation technique is proposed to automatically adjust the slew rate of a 2×VDD output buffer. Based on the detected PVT (Process, Voltage, Temperature) corner, the output buffer will turn on different current paths correspondingly to either increase or decrease the output driving current such that the slew rate of the output can be adjusted as well. The proposed design is implemented using a typical 40 nm CMOS process to justify the slew rate compensation performance. By on-silicon measurements, the data rate is 500/460 MHz given 0.9/1.8 V supply voltage with a 20 pF load, the maximum slew rate is 0.53 (V/ns), and the core area of the proposed design is 0.052 × 0.254 mm2.

This work presents a digital over-temperature protector for FlexRay systems. A temperature sensor with a negative coefficient with respect to frequency is realized on silicon. A frequency to digital converter (FDC) is used to convert the frequency into a digital code to represent the sensed temperature. An experimental prototype was implemented using a typical 0.35 μm CMOS process. The post-layout-extracted simulation results reveal that the worst error is less than ±6°C at all PVT (Process, voltage, and temperature) corners. Notably, the error is less then ±1.8°C in the range from 0°C to 100°C.

A fast protein concentration measurement system with two-port FPW (flexural plate wave) biosensors using a frequency-shift readout technique is presented in this paper. The proposed frequency-shift readout method employs a peak detecting scheme to measure the amount of resonant frequency shift. The frequency sweep range of the linear frequency generator is limited in 2 MHz to 10 MHz according to the characteristics of the FPW biosensors. The proposed frequency-shift readout circuit is verified on silicon using a standard 0.18 μm CMOS technology. The power consumption of the proposed protein concentration measurement system is 48 mW given a 0.1 MHz system clock. The protein concentration measurement is read out in less than 10 minutes.

This paper presents an Automatic Gain Control (AGC) circuit with 200 to 530 μW average power consumption given a 1 V supply. The Variable Gain Amplifier (VGA) therein comes with 0.9 V input and output stages with a minimum bandwidth of 100 MHz. Feed-forward Output Swing Prediction is used to adjust the gain of the VGA corresponding to the signal envelope detected by a Parallel-Detect Singular-Store Peak Detector. With an appropriate refresh-rate control, the AGC is capable of adjusting the gain of the VGA within less than 250 ns when the input signal envelope is reduced by 20 dB, and 100 ns when raised by 20 dB. The circuit design is carried out using a 0.18 μm standard CMOS process with a core area of 0.0024 mm2.

This paper presents a high speed transceiver design with fault detection circuit compliant with FlexRay standards V2.1. An LVDS-like transmitter is utilized to drive the twisted pair of the bus. A current detector is included in the transceiver to detect the operating current so as to prevent over-current hazard. By contrast, a 3-comparator scheme is used to carry out the required bit-slicing and state recognition in the receiver of the bus. A bus line short-circuit detector is also included in the proposed receiver design.

A 60 V battery charger implemented using TSMC 0.25 μm Bipolar-CMOS-DMOS (BCD) 60 V process is presented in this work. A novel transition method is proposed to ensure smooth transitions between constant current (CC) and constant voltage (CV) modes. Since the proposed approach would require only additional diodes, power consumption and chip area are conserved in comparison with other sophisticated methods proposed in prior works. The charger sources a current of 50 mA in CC mode and has an efficiency of 75% ~ 80% throughout the charging sequence. The supply voltage is kept at 3 volts higher than the battery voltage throughout the charging sequence to maintain charging efficiency. A thermal protection circuit is included in this design to prevent the charger from operating at a temperature over the maximum allowed temperature.

A fully bidirectional mixed-voltage input/output (I/O) buffer using a novel floating N-well circuit is presented. To provide appropriate gate voltages for output stage transistors, a dynamic gate bias generator without gate-oxide overstress effect is implemented. The proposed I/O also takes advantage of a novel gate-tracking circuit and a PAD voltage detector by means of eliminating the leakage current such that the compatibility among all subcircuits is ensured. Our design is proved on silicon using 0.18 μm CMOS process that when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, the maximum data rate is found to be 80/80/125/100/80 MHz, respectively, with a given capacitive load of 10 pF.

A mini-invasive system ASIC for multiple bladder pressure measurement function is presented. Not only can the period of measurement be adjusted, the flexibility is also enhanced by using a tunable IA (instrumentation amplifier). Because the pressure inside the body cavity (i.e., bladder) usually does not vary drastically, a long-term mode is required to save the battery power for a reliable observation. Besides, the pressure dynamics in a cavity also could be examined in the continuous mode. The IA amplifies the signal sensed by the pressure sensor, which is then fed into the following ADC (analog-to-digital converter). Owing to the intrinsic 1-atm pressure (one atmospheric pressure) existing inside the body cavity and the various resolution requirement for the different applications, the input range of the IA must be able to be adjusted to keep the required linearity. The pressure range of the proposed system is found out to be 10.4~27.7 Psi with the maximum resolution of 8.42 × 10-4Psi, which is more than enough for most of pressure measurement applications.

A fully bidirectional mixed-voltage I/O buffer using a gated Floating N-well circuit is presented. In addition, to provide appropriate gate voltages for Output stage, a Dynamic gate bias generator without gate-oxide overstress effect is implemented. The proposed I/O also takes advantage of a novel Gate-tracking circuit and a PAD voltage detector by means of eliminating the leakage current such that the compatibility among all subcircuits is ensured. Our design is proved on silicon that when VDDIO is 5.0/3.3/1.8/1.2/0.9 V, the maximum data rate is found to be 80/80/125/100/80 MHz, respectively, with a given capacitive load of 10 pF.

This paper proposed an complementary all-N-transistor (CANT) comprising ANT logic and inverted ANT logic. In ANT logic's N-Block, the threshold voltage of the transistors is variable depending on the operation of the entire logic block. In the evaluation phase, the bulk voltage of the transistors in the N-Block is increased to VDD-Vthnto enhance the operation speed. In the pre-charge phase, the bulk voltage of the transistors in the N-Block is dropped to almost 0 V such that the subthreshold leakage current is reduced. By utilizing such a variable bulk voltage scheme in the proposed complementary ANT (CANT) logic, a 32-bit CLA is designed using TSMC 90 nm CMOS process to verify the low power and high speed performance. The area of the proposed design is 0.0483 mm2and the power dissipation is 102 mW given a 7.2 GHz clock at the worst PVT condition.

This paper presents a high frequency low harmonics content AC source consisted of two phase shifted resonant legs, suitable for driving piezoelectric devices such as those employed in ultrasound radiators. The inverter is characterized by high efficiency, low harmonic distortion, good dynamic response, and simplicity of load power control. Particularly low harmonic content is attained by the proper phase shift between the two inverter legs.

This paper presents a low power digital multiplier design by taking advantage of a 2-dimensional bypassing method in cell-based design flow. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Thorough cell-based design flow post-layout simulations show that the power delay product of the proposed 8×8 multiplier design is reduced by more than 13.8% compared to prior designs.

An adaptive refreshing circuitry design for DRAMs is presented in this work. The proposed refreshing circuitry uses a voltage comparator to monitor the voltage drop caused by the data loss of a memory cell that results from leakage currents in order to dynamically adjust the refreshing period of the memory cell. Besides, a process variation monitor is also included in the proposed design to compensate the process drifting problem. Therefore, the proposed design is insensitive to temperature variations as well as process drifts. The period of the refreshing clock is automatically adjusted to save a great portion of standby power of DRAMs. A 4-Kb DRAM is implemented by a typical 0.13-mum 1P8M digital CMOS process. The post-layout simulation verifies the correctness of the adaptive refreshing cycles generated by the proposed design.

A mini-invasive system for different purposes of the bladder urine pressure measurement is presented. Not only can the period of measurement be adjusted, the flexibility is also enhanced by using a variable IA (instrumentation amplifier). Because the urine pressure inside the bladder usually does not vary drastically, a long-term mode is required to save the battery power for a reliable observation. Besides, the pressure dynamics in a bladder also could be examined in the continuous mode. The IA amplifies the signal sensed by the pressure sensor, which is then fed into the following ADC (analog-to-digital converter). Owing to the intrinsic 1-atm pressure (one atmospheric pressure) existing inside the bladder and the various resolution requirement for the different applications, the input range of the IA must be able to be adjusted to keep the required linearity. The pressure range of the proposed system is found out to be 10.4 ~ 27.7 Psi with the maximum resolution of 6.75 x 10-3, which covers the range of all of the known unusual bladder syndromes or complications.

This paper presents an architecture as well as circuit implementation of a ZigBee modulator/demodulator in the transceiver for personal area network, which is compliant with the physical layer of IEEE standard 802.15.4. A test prototype has been designed and fabricated using 0.18-mum single-poly six-metal CMOS process with core area of 0.16 mm2. The measurement results show that packet error rate (PER) is less than 1% given SNR = 5 dB. The total power consumption is merely 251 muW at a 2.4-MHz system clock.

A high speed and low power 8-bit carry-lookahead adder using two-phase modified dual-threshold voltage (dual-Vt) domino logic blocks which are arranged in a programmable logical array-like design style with pipelining is presented. The modified domino logic circuits employ dual-transistors and reversed bulk-source biases for reducing subthreshold leakage current when advanced deep submicrometer process is used. Moreover, an nMOS transistor is inserted in the discharging path of the output inverter such that the modified domino logic can be properly applied in a pipeline structure to reduce the power consumption. The addition of two 8-bit binary operands is executed in two cycles. Not only is it proven to be also suitable for long adders, the dynamic power consumption is also drastically reduced by more than 10% by the measurement results on silicon.

An implantable system for long-term bladder urine pressure measurement system is presented. Not only is the design cost reduced, but also the reliability is enhanced by using a 1-atm canceling sensing IA (instrumentation amplifier). Because the urine pressure inside the bladder does not vary drastically, both the sleeping and working modes are required in order to save the battery power for long-term observation. The IA amplifies the signal sensed by the pressure sensor, which is then fed into the following ADC (analog-to-digital converter). Owing to the intrinsic 1-atm pressure (one atmospheric pressure) existing inside the bladder, the IA must be able to cancel such a pressure from the signal picked up by the pressure sensor to keep the required linearity and the resolution for pressure measurement of the bladder urine. The pressure range of the proposed system is found out to be 14.7 ~ 19.7 Psi, which covers the range of all of the known unusual bladder syndromes or complications.

A low-power sensorless inverter controller is designed for brushless DC (BLDC) motors without using any Hall sensor. A back-EMF (back-electromotive force) estimation method is adopted to detect the commutation moment for rotation control of the brushless DC motors. The position of the rotor can be precisely estimated by measuring the back-EMF as well as the zero-crossing points. The proposed controller is low power and low cost because of not using expensive power consuming Hall sensors. The proposed sensorless inverter controller is integrated in a standard mixed-signal single-poly, and six metal 0.18-μm CMOS process.

This paper presents architecture as well as the circuit implementation of a ZigBee transceiver using 868/915 MHz band, which is compliant to the physical layer of IEEE 802.15.4. Two low-power analog-to-digital converters (ADC) are integrated within the proposed transceiver. The ADC is a 5-bit SA-based (successive approximation) structure. The post-layout simulation shows the packet error rate (PER) is less than 1% given SNR = 5 dB. The overall power consumption is merely 6.57 mW (Tx power = 3.28 mW, Rx power= 3.29 mW)

The physical implementation of a prototypical 250-MHz CMOS 4-T SRAM is described in this paper. The proposed SRAM cell takes advantage of a negative word-line gate drive to minimize the leakage current of the cell access transistors. As a result, the standby power consumption is drastically reduced. The proposed 4-Kb 4-T SRAM is measured to consume 0.12 mW in the standby mode, and a 3.8 ns access time in the R/W mode. The highest operating clock rate is measured to be 263 MHz.

Various implantable microstimulators have been proposed for clinical applications in recent years. Most of the no-battery implanted devices can be powered by a transcutaneous magnetic coupling, which basically utilizes an external transmitter coil to power and communicate with the implanted device. Small chip area and low power consumption are the keys of the implanted device. Therefore, we propose a C-less (no capacitor) area-saving ASK demodulator in this work to get rid of those large discrete capacitors required for low-frequency ASK demodulation. Additionally, a power regulator supplying a stable VDD/spl I.bar/OUT is also built in to resolve the unstable supply voltage problem resulted from the inductive link. Besides, a multiparameter control protocol which has an area advantage over microcontroller-based solutions is also proposed for various pain treatments of muscles and stimulating applications.

This paper presents a practical self-recharging circuitry for DRAMs. The proposed self-recharging circuitry not only reduces the standby power by monitoring the voltage drop caused by the data loss of a memory cell but also adjusts the recharging period of the memory cell that results from leakage currents. The proposed design is insensitive to temperature variations. A 1-Kb DRAM using our design is fabricated by a TSMC 0.35-/spl mu/m 1P4M CMOS process. The physical measurement of the proposed design on silicon verifies the correctness of the proposed circuitry.

The design and physical implementation of a prototypical 500-MHz CMOS 4-T SRAM is presented in this work. The latch of the proposed SRAM cell is realized by a pair of cross coupled high-V/sub THP/ pMOS transistors, while the bitline drivers are realized by a pair of low-V/sub THN/ nMOS transistors. The wordline voltage compensation circuit and bitline boosting circuit, then, are neither needed to enhance the data retention of memory cells. Built-in self-refreshing paths make the data retention possible without the appearance of any external refreshing mechanism. The advantages of dual threshold voltage transistors can be used to reduce the access time, and maintain data retention at the same time. Besides, a new design of cascaded noise-immune address transition detector is also included to filter out the unwanted chip select glitches when the SRAM is asynchronously operated.

A CMOS local oscillator using a programmable delayed-lock loop based frequency multiplier is present in this paper. The maximum measured output frequency is 1.2 GHz. The frequency of the output clock is 8/spl times/ to 10/spl times/ of an input reference clock between 100 to 150 MHz at simulation. No LC-tank is used in the proposed design such that the power dissipation as well as the active area is drastically reduced. The design is carried out by TSMC 1P5M 0.25 /spl mu/m CMOS process at 2.5 V power supply. The average lock time is optimally shortened by initializing the start-up voltage of the voltage-controlled delay tap line at the midway of the working range. Meanwhile, the power dissipation is 52.5 mW at 1.2 GHz output.

A ROM-less direct digital frequency synthesizer employing trigonometric quadruple angle formula is present in this paper. The worse case spectral purity is better than -130 dBc. The amplitude resolution is up to 13 bits, while the phase resolution is 12 bits. Neither any scaling table nor error correction tables are required. The maximum error is mathematically analyzed. The word length of each multiplier is carefully selected in the digital implementation such that the error range is circumscribed and the resolution is preserved.

Read-only memories (ROMs) are widely used in both digital communication systems and daily consumer electronics. The major functions of ROMs are storage of data, programs, firmwares, etc. In this paper, a three-dimensional decoding structure for ROMs is proposed. The number of address decoding stages is drastically shortened. Hence, the delay is reduced, as well as the power consumption and area. The analysis of overall transistor count and delay is thoroughly derived. A real 256 /spl times/ 8 ROM possessing the proposed decoder is physically fabricated by 0.5-/spl mu/m two-poly two-metal (2P2M) CMOS technology.

In new generations of microprocessors, the superscalar architecture is widely adopted to increase the number of instructions executed in one cycle. The division instruction among all of the instructions needs more cycles than the rest, e.g., addition and multiplication. This makes the division instruction an important cycles-per-instruction figure for modern microprocessors. In this paper, a radix-16/8/4/2 divisor is proposed, which uses a variety of techniques, including operand scaling, table partitioning, and, particularly, table sharing, to increase performance without the cost of increasing complexity. A physical chip using the proposed method is implemented by 0.35-/spl mu/m single poly four metal (1P4M) CMOS technology. The testing measurement shows that the chip can execute signed 64-b/32-b integer division between 3-13 cycles with a 80-MHz operating clock.

A novel method of pattern recognition using Polynomial Bidirectional Hetero-Correlator (PBHC) is proposed. Simulation results show that the new scheme displays superior storage capacity over other BAM-like associative memories and fuzzy associative memories.

The Programmable Logic Arrays (PLAs) have become popular devices in realization of both combinational and sequential circuits. We present a power-saving fast half-swing CMOS circuit implementation for NOR-NOR PLA implementation. An additional 1/2 VDD voltage source and buffering transmission gates are inserted between the NOR planes to erase the racing problem and shorten the rise delay as well as the fall delay of the output response such that the speed is enhanced and the dynamic power is reduced.

In this work, improved designs of 3-2 C/sup 2/PL-based compressors are presented which can be used to build a fast inner product processor. The features of our compressors include a short delay minimized by HSPICE optimization, less transistor count, and high fan-out.

In this paper, we propose a 64-bit fast dynamic CMOS comparator with a small transistor count. Major features of the proposed comparator are the rearrangement and re-ordering of transistors in the evaluation block of a dynamic cell, and the insertion of a weak n feedback inverter, which helps the pull-down operation to ground. The simulation results given by prelayout tools, e.g., HSPICE, and post-layout tools, e.g., TimeMill reveal that the delay is around 2.5 ns while the operating clock rate reaches 100 MHz.

The multi-valued exponential bidirectional associative memory (MV-eBAM) has been proposed and proved to be asymptotically stable under certain constraints. Although multi-valued eBAM has been verified to possess high capacity by thorough simulations, the capacity is still unable to be solved analytically. In the paper, an algorithm is proposed to derive the capacity. Some important characteristics, including the absolute lower bound of the radix, and the approximate capacity are also discussed. The result shows that the multi-valued eBAM indeed possesses high capacity.

A method of fuzzy data recall using polynomial bidirectional hetero-correlator is presented. This has a higher capacity for pattern pair storage than that of the conventional BAMs and fuzzy memories. A new energy function is defined. The polynomial bidirectional hetero-correlator (PBHC) takes advantage of fuzzy characteristics in evolution equations such that the signal-noise-ratio (SNR) is significantly increased. In this work, we prove the stability of fuzzy data recall using polynomial bidirectional hetero-correlator. The increase of SNR consequently enhances the capacity of the polynomial bidirectional hetero-correlator. The capacity of the fuzzy data recall using PBHC in the worst case is also estimated.

A novel data compression algorithm utilizing the histogram and the high-capacity exponential bidirectional associative memory (eBAM) is presented. Since eBAM has been proved to possess high capacity and fault tolerance, it is suitable to be utilized in the data compression using the table-lookup scheme. The histogram approach is employed to extract the feature vectors in the given data. The result of the simulation of the proposed algorithm turns out to be better than the traditional methods.

The exponential bidirectional associative memory (eBAM) has been proposed and proved to be a stable and high capacity associative neural network. However, the intrinsic structure and the evolution functions of this network restrict the representation of patterns to be either bipolar or binary vectors. We consider the promising development of multi-valued systems and then design a multi-valued discrete eBAM (MV-eBAM). The multi-valued eBAM has been proved to be asymptotically stable under certain constraints. Although MV-eBAM is also verified to possess high capacity by thorough simulations, there are important characteristics to be explored, including the absolute lower bound of the radix, and the approximate capacity. In order to estimate the capacity of the MV-eBAM, a modified evolution equation is also proposed. Hence, an analytic solution is derived. Besides, a radix searching algorithm is presented such that the absolute lower bound of the radix for this MV-eBAM can be found.

The asymptotical stability of exponential bidirectional associative memory (eBAM) has been proved based on the systematic stability of the exponential correlation associative memory (ECAM). Although the eBAM has also been proved to possess high capacity, the hardware realization still remains an issue mainly due to the implementation of the necessary exponential function. Considering the practical problems, we employ the current-mode implementation using the exponential I-V characteristic of the MOS diode circuit to realize the eBAM. The proposed architecture for the implementation turns out to be a scalable, regular, and dense design.

An exponential bidirectional associative memory (eBAM) using an exponential encoding scheme is discussed. It has a higher capacity for pattern pair storage than conventional BAMs. A new energy function is defined. The associative memory takes advantage of the exponential nonlinearity in the evolution equations such that the signal-to-noise ratio (SNR) is significantly increased. The energy of the eBAM decreases as the recall process proceeds, ensuring the stability of the system. The increase of SNR consequently enhances the capacity of the BAM. The capacity of the exponential BAM is estimated.

A method for modeling the learning of belief combination in evidential reasoning using a neural network is presented. A centralized network composed of multiple exponential bidirectional associative memories (eBAM's) sharing a single output array of neurons is proposed to process the uncertainty management of many pieces of evidence simultaneously. The stability of the proposed multiple eBAM network is proved. The sufficient condition to recall a stored pattern pair is discussed. Most important of all, a majority rule of decision making in presentation of multiple evidence is also found by the study of signal-noise-ratio of multiple eBAM network. A guaranteed stable state condition, i.e., the condition for the fastest recall of a pattern pair, is also studied. The result is coherent with the intuition of reasoning.