This paper presents Simultaneous Speculative Threading (SST), which is a technique for creating high-performance area- and power-efficient cores for chip multiprocessors. SST hardware dynamically extracts two threads of execution from a single sequential program (one consisting of a load miss and its dependents, and the other consisting of the instructions that are independent of the load miss) and executes them in parallel. SST uses an efficient checkpointing mechanism to eliminate the need for complex and power-inefficient structures such as register renaming logic, reorder buffers, memory disambiguation buffers, and large issue windows. Simulations of certain SST implementations show 18% better per-thread performance on commercial benchmarks than larger and higher-powered out-of-order cores. Sun Microsystems' ROCK processor, which is the first processor to use SST cores, has been implemented and is scheduled to be commercially available in 2009.

No abstract available.

The traditional balance between processor clock rate and instruction level parallelism (ILP) has been severely shaken due to enablers and constraints that were not prevalent or did not exist during the last two decades. With the current broad deployment of multithreaded software for servers (increasing rapidly for desktops), a traditional processor, e.g. with high frequency and traditional OoO scheduling, is no longer optimal to extract performance. Moreover as cache footprints grow due to problem size, scaling, and multiprogramming, the memory wall problem is only getting worse. Not to be forgotten is Amdahl's law, which in this context of, on-chip closely-coupled parallel execution, makes single-thread performance important since even a small fraction of non-scalable code affects overall performance. Other constraints such as power density and overall power limitation for air- and liquid-cooled systems make putting multiple traditional cores on a single die an unattractive design point. High-Performance Throughput Computing, achieved through design-from-scratch processors composed of multiple multithreaded cores, offers an unprecedented opportunity to create a new generation pipeline that delivers both high throughput performance and high single-thread performance. This is the first disclosure of what we believe is the first truly new pipeline in a decade. A checkpoint-based architecture that offers a new execution model will be described. Hardware threads are spawned and they speculatively execute and retire instructions out-of-order. Power efficiency is emphasized by maximizing the utilization of pipeline stages through temporal threading and functional units through spatial threading and speculation. This pipeline is embedded multiple times in our future high-end 65nm and 45nm processors that form the cornerstone a broad line of systems ranging from small servers to supercomputers.

Article Free Access Share on A fast and flexible performance simulator for micro-architecture trade-off analysis on UltraSPARC-I Authors: Marc Tremblay SPARC Technology, Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CA SPARC Technology, Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CAView Profile , Guillermo Maturana SPARC Technology, Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CA SPARC Technology, Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CAView Profile , Atsushi Inoue SPARC Technology, Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CA SPARC Technology, Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CAView Profile , Les Kohn SPARC Technology, Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CA SPARC Technology, Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CAView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 2–6https://doi.org/10.1145/217474.217479Published:01 January 1995Publication History 10citation307DownloadsMetricsTotal Citations10Total Downloads307Last 12 Months13Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF

The realization of a high performance modern microprocessor involves hundreds of person-years of conception, logic design, circuit design, layout drawing, etc. In order to leverage effectively the 5-10 millions of transistors available, careful microarchitecture tradeoff analysis must be performed. This paper describes not only the microarchitecture of UltraSPARC-I, a 167 MHz 64-b four-way superscalar processor, but more importantly it presents the analysis and tradeoffs that were made "en route" to the final chip. Among several issues, the in-order execution model is compared with alternatives, variations of the issue-width of the machine as well as the number of functional units are described, subtle features that are part of the memory hierarchy are explained, and the advantages of the packet-switched interconnect are exposed.

This paper presents a sensing approach where photo-transduction, multi-resolution feature extraction, scale-space integration and edge tracking are performed on a mixed (digital-analog) VLSI architecture in order to generate medium-level scene description. The proposed system is mainly targeted for robot vision applications where feature description is preferred to a set of raw or raster 2D images and edge maps. The Multiport Access photo-Receptor (MAR) is a CMOS sensor and represents the main sensory part of this integrated image acquisition system. VLSI also provides means to integrate analog computing, digital controller and DSP co-processor modules which define a powerful sensory chip set for focal plane image processing. A current version of the MAR sensor which implements 256/spl times/256 pixels includes 16 analog spatial filters which simultaneously compute multiresolution edge maps. This unique 2D hexagonal smart sensor approach which performs up to 8.5/spl times/10/sup 9/ arithmetic Op/sec during the acquisition/filtering phase and 25/spl times/10/sup 9/ Logical Op/sec for scale-space integration allows high resolution image capability. It represents a significant improvement for passive sensory units in a compact assembly for computer vision applications.>

The complexity of information extraction requires the development of efficient and dedicated hardware systems designed to operate in harmony with robot vision and automation. This paper describes a system which combines optical sensing with integrated focal-plane processing capabilities and integrated image post-processing. It is capable of automatic edge tracking and returns lists of connected pixels. I. INTRODUCTION Autonomous robotic applications require the use of reliable sensors since the capability to extract meaningful information from the surrounding environment is paramount to the accomplishment of any task. Among all sensing modalities, computer vision is the one that is most naturally associated with autonomous robotics. This originates from the fact that visual information can provide a very rich semantic description of the world. Vision operates through a process of successive refinements. The illuminance recorded at each component of the retina is processed, and low-level features such as edges and regions are extracted through relatively simple operations. Higher-level percepts such as depth and motion parameters can then be obtained from these low-level features. A very effective approach to the extraction of edges is based on the convolution of circularly symmetric masks with the illuminance image El). Among the available circularly symmetric masks is the well-known Laplacian of Gaussian (LOG) expressed as:

The Multiport Array Receptor (MAR), a system which combines optical sensing with integrated focal-plane processing capabilities, is described. Its central element is a photosensor array with hexagonal tesselation and complex peripheral selection logic which provides parallel analog readout over prescribed areas. An external computing module performs real-time spatial convolution at multiple resolutions while a closed-loop microprogrammed controller addresses regions of interest and supervises communication between the camera and the host computer. This integrated image sensor and processor implements programmed sequences of instruction primitives and yields a complete state description of each processed pixel. It is capable of automatic edge tracking and returns lists of connected pixels.>

A technique called micro rollback, which allows most of the performance penalty for concurrent error detection to be eliminated, is presented. Detection is performed in parallel with the transmission of information between modules, thus removing the delay for detection from the critical path. Erroneous information may thus reach its destination module several clock cycles before an error indication. Operations performed on this erroneous information are undone using a hardware mechanism for fast rollback of a few cycles. The implementation of a VLSI processor capable of micro rollback is discussed, as well as several critical issues related to its use in a complete system.>