Wireless network nodes working in industrial environment or mounted on mobile machines are exposed to frequent and unpredictable temperature changes, which impact local clock accuracy resulting in synchronization problems (time offset). These issues have to be taken into account when optimizing the network to avoid higher energy consumption and traffic congestion. The time offset problem can be alleviated using temperature driven compensation. In the paper we propose an efficient algorithm to resolve this problem taking into account slow and rapid temperature fluctuations. It combines the physical model of the node oscillator with an original prediction method based on the linear regression. It can be embedded in low cost microcontrollers with limited resources. Our approach needed some experimental studies of oscillator features and microcontroller capabilities. The implemented prototype nodes and performed tests proved high clock resilience for industrial environment as compared with other approaches.

Performance monitoring and anomaly detection are major issues in designing and maintaining electronic devices and systems. In recent years, they become more difficult due to the increased complexity of hardware and software. Hence, an important point is to collect representative signal samples and reveal characteristic features allowing to evaluate device operational profiles. This results in the need of an efficient time series analysis. This problem is considered in relevance to embedded systems and Internet of Things devices. The paper presents a new scheme of decomposing time series by introducing higher level objects targeted at the searched system properties. They create a compact state model which facilitates deriving knowledge on system behaviour to validate correctness of its operation. The collected samples are aggregated into objects according to predefined similarity metrics, these objects can be traced, correlated, and merged with relevant operational log events. For this purpose, a set of original algorithms have been composed and included in the developed software tool. The presented approach has been evaluated on a representative dataset obtained from commercial Holter devices and was used to explore their energy consumption efficiency.

The paper presents the new software library supporting development of the fault-robust applications. The main goals of the proposed software hardening mechanisms are: usage simplicity for the programmer, independence from the development tool, effectiveness in terms of fault coverage, low static and dynamic overheads. The paper describes implemented software mechanisms and discusses their effectiveness verified with fault injection experiments.

The paper addresses the problem of creating a comprehensive fault injection environment, which integrates and improves various simulation and supplementary functions. This is illustrated with experimental results.

The paper addresses the problem of evaluating the effectiveness of fault hardening procedures based on software redundancy. We analyze the time and memory overhead of fine-grained and coarse-grained error detection and correction techniques. We check the impact of the involved overhead on fault coverage. The presented considerations are illustrated with fault injection experimental results.

The paper addresses the problem of evaluating transient fault impact on COTS microprocessor systems. We present the problem of fault effect propagation from low logical to software and application levels. Such an analysis is needed to optimize error detection and correction mechanisms at hardware and software levels. For this purpose we use sophisticated fault injectors. The usefulness of the presented approach was proved in many experiments described in the paper. It may support hardware/software co-design.

The problems of hardware fault detection and correction using software techniques are analysed. They relate to our experience with a large class of applications. The effectiveness of these techniques is studied using a special fault injector with various statistical tools. A new error-handling scheme is proposed.

We investigate program susceptibility to hardware faults in Win32 environment. For this purpose we use the software implemented fault injector FITS. We analyze natural fault resistivity of COTS systems and the effectiveness of various software techniques improving system dependability. The problems of experiment tuning and result interpretation are discussed in context of a wide spectrum of applications.

The paper addresses the problem of evaluating CPU performance in real system environment. We present an efficient methodology of CPU performance analysis at the architecture (coarse grained) and microarchitecture (fine grained) levels. It is based on time and internal event monitoring technique. This methodology is referred to Intel processors operating in IBM PC environment. The usefulness of the presented approach was proved in many experiments described in the paper.

Summary form only given. Arithmetic coprocessors (AC) are quite complex circuits and testing them is an important and not easy problem (not covered in the literature). Analyzing diagnostic software for IBM PCs we found that the testing procedures for ACs are limited to simple basic checks. Hence we decided to develop efficient test procedures in a systematic way. They are executed on the main processor and generate appropriate stimuli to AC functional blocks (e.g. instruction sequencer, data path units) and verify test responses. An important contribution of this paper is the integration of various approaches to testing and increased test observability of test results assured by on-chip event monitors and system exceptions.

Caches embedded in microprocessor systems are implemented with limited observability and controllability. Hence they create many problems in testing. This paper gives a methodology of developing user test programs for data and instruction caches with various organization.

In this paper we present an original technique of testing classical RAMs (without BIST) in real system environment. The developed testing methodology allows to cover a large class of faults including pattern sensitivity and dynamic faults. An important feature of the presented approach is test transparency which assures that at the end of the test the contents of the RAM are equal to its initial contents (before testing). This technique is especially useful for periodic autodiagnostic procedures in embedded and multiprocessor systems. It has been also extended for cache and dual port RAMs.>

An approach is presented to the online detection of control flow errors caused by transient and intermittent faults in microprocessor systems. It is based on the idea of signatured instruction streams. Signatures are embedded into the program memory using the monitored processor instructions. Compared with existing techniques, the presented approach is universal and can be easily implemented using off-the-shelf programmable array logic and LCA circuits. The hardware overhead ranges from one to several chips for microprocessors with 8-bit and 16-bit data buses. Program memory overhead is 10-20% and quite often no extra memory chip is required. A special software module has been developed to embed signatures and checkpoints into application programs.>