A circuit analysis method, the hierarchical waveform relaxation technique, that uses multilevel decomposition and relaxation techniques is presented. Sufficient conditions for the convergence of the process are discussed, and a dynamic circuit restructuring technique that uses the concept of sensitivity based subcircuit merging and repartitioning within the hierarchical framework to improve the robustness of the simulation algorithm as well as the speed of convergence is presented. The algorithm is implemented in the circuit simulation program PYRAMID, and test results are compared with those obtained by other methods of analysis. The comparison indicates that this method produces better results than had previously been possible for a large range of circuits of practical interest, particularly strongly coupled digital bipolar and FET circuits containing bidirectionality and feedback, and it is demonstrated that the relative improvement of the method scales with the size of the circuit.>

A hierarchical waveform-relaxation-based method for analysis of bipolar, MOS, and GaAs FET circuits is presented. By analyzing the circuit in a hierarchical manner, a faster solution has been obtained for circuits exhibiting strong bidirectionality and feedback than has previously been possible. The technique has been applied to a wide variety of digital and mixed analog/digital circuits, and circuits containing over 18000 transistors have been analyzed. Results obtained for a variety of circuits show up to two orders of magnitude improvement in computation time compared to conventional circuit simulation techniques and up to one order of magnitude improvement compared to the standard waveform-relaxation technique.>