In this paper, we propose a new testability metric for path delay faults.The metric is computed efficiently using a non-enumerative algorithm.It has been validated through extensive experiments and the results indicate a strong correlation between the proposed metric and the path delay fault testability of the circuit.We further apply this metric to derive a path delay fault test application scheme for scan-based BIST.The selection of the test scheme is guided by the proposed metric.The experimental results illustrate that the derived test application scheme can achieve a higher path delay fault coverage in scan-based BIST.Because of the effectiveness and efficient computation of this metric, it can be used to derive other design-for-testability techniques for path delay faults.

Static property checking verifies pre-defined functional design rules such as "bus contention", "racing condition"; and "don't-care case". A static property checker typically uses formal verification techniques to prove the property under verification. If the property is proven false, a counter-example is generated for debugging the design. Among the different static property checking approaches, ATPG-based and BDD-based are the most powerful and successful ones. We implement both approaches with several optimization techniques on the same framework to compare their performance. The experimental results on industrial designs show that these two approaches have different strength and weakness in proving the static properties. Furthermore, the results indicate that they often complement each other and therefore a hybrid approach may result in better performance. We propose a static property checker based on combined ATPG and BDD techniques. The experimental results show that this combined approach can prove all the static properties in the test cases while still maintaining comparable performance.

In this paper, we explore two techniques, under the existing scan-based built-in self-test (BIST) architectures, for improving the test quality with practically no additional overhead. The proposed techniques are an almost-full-scan BIST strategy and a general scan-based BIST test application scheme. We first demonstrate that under the scan-based BIST architecture, full scan may not result in the highest fault coverage (FC) and unscanning a small number of scan flip-flops may increase the BIST FC. We then present an algorithm for identifying those not-to-be-scanned flip-flops. We further show that the proposed general scan-based BIST test application scheme could also result in higher BIST FC and only requires a minor modification to the BIST controller. Experiments have been conducted using an industrial tool, psb2, on benchmark circuits to illustrate the effectiveness of the proposed techniques and algorithms. The results have demonstrated that both techniques are able to maximize the FC and reduce the test application time without additional test hardware compared to the conventional scan-based BIST architectures.

In this paper, we propose a general test application scheme for existing scan-based BIST architectures.The objective is to further improve the test quality without inserting additional logic to the Circuit Under Test (CUT).The proposed test scheme divides the entire test process into multiple test sessions.A different number of capture cycles is applied after scanning in a test pattern in each test session to maximize the fault detection for a distinct subset of faults.We present a procedure to find the optimal number of capture cycles following each scan sequence for every fault.Based on this information, the number of test sessions and the number of capture cycles after each scan sequence are determined to maximize the random testability of the CUT.We conduct experiments on ISCAS89 benchmark circuits to demonstrate the effectiveness of our approach.

This paper illustrates that for existing scan-based Built-In Self-Test (BIST) architectures under the pseudo-random testing scheme, scanning all flip-flops may not be the best strategy for achieving high fault coverage with a practical limit on test length. In general, for scan-based BIST, not scanning flip-flops with relatively high pseudo-random observabilities through the primary outputs may indeed improve the fault coverage as well as the test application time. We illustrate the issues and present a flip-flop selection strategy for scan-based BIST to maximize the fault coverage and reduce the test application time. Experiments have been conducted based on an industrial tool psb2 for several benchmark circuits. The results show that the almost-full-scan circuits based on our flip-flop selection strategy can achieve higher fault coverages and significantly shorter test application time as compared with the full-scan circuits.

We propose a test point selection algorithm for scan-based built-in self-test (BIST). Under a pseudorandom BIST scheme, the objectives are (1) achieving a high random pattern fault coverage, (2) reducing the computational complexity, and (3) minimizing the performance as well as the area overheads due to the insertion of test points. The proposed algorithm uses a hybrid approach to accurately estimate the profit of the global random testability of a test point candidate. The timing information is fully integrated into the algorithm to access the performance impact of a test point. In addition, a symbolic procedure is proposed to compute testability measures more efficiently for circuits with feedbacks so that the test point selection algorithm can be applied to partial-scan circuits. The experimental results show the proposed algorithm achieves higher fault coverages than previous approaches,with a significant reduction of computational complexity. By taking timing information into consideration, the performance degradation can he minimized with possibly more test points.

We propose a new algorithm for test point selection for scan-based BIST. The new algorithm combines the advantages of both explicit-testability-calculation and gradient techniques. The test point selection is guided bya cost function which is partially based on explicit testability recalculation and partially on gradients. With an event-driven mechanism, it can quickly identify a set of nodes whose testability need to be recalculated due to a test point, and then use gradients to estimate the impact of the rest of the circuit. In addition, by incorporating timing information into the cost function, timing penalty caused by test points can be easily avoided. We present the results to illustrate that high fault coverages for both area- and timing-driven test point insertions can be obtained with a small number of test points. The results also indicate a signi#cant reduction of computational complexity while the qualities are similar to the explicitly-testability-calculation method. 1 I...