In recent years 360° videos have been becoming more popular. For traditional media presentations, e.g., on a computer screen, a wide range of assessment methods are available. Different constructs, such as perceived quality or the induced emotional state of viewers, can be reliably assessed by subjective scales. Many of the subjective methods have only been validated using stimuli presented on a computer screen. This paper is using 360° videos to induce varying emotional states. Videos were presented 1) via a head-mounted display (HMD) and 2) via a traditional computer screen. Furthermore, participants were asked to rate their emotional state 1) in retrospect on the self-assessment manikin scale and 2) continuously on a 2-dimensional arousal-valence plane. In a repeated measures design, all participants (N = 18) used both presentation systems and both rating systems. Results indicate that there is a statistically significant difference in induced presence due to the presentation system. Furthermore, there was no statistically significant difference in ratings gathered with the two presentation systems. Finally, it was found that for arousal measures, a statistically significant difference could be found for the different rating methods, potentially indicating an underestimation of arousal ratings gathered in retrospect for screen presentation. In the future, rating methods such as a 2-dimensional arousal-valence plane could offer the advantage of enabling a reliable measurement of emotional states while being more embedded in the experience itself, enabling a more precise capturing of the emotional states.

In this paper we consider using memristors for high-dimensional computing that requires very large associative memories, but generally has good tolerance to nonidealities in the implementation medium. To consider such computing with existing devices, we present measurements of a tantalum oxide memristor that can be programmed to resistance values between high resistance state and low resistance state. Based on the measurements, we estimate the variation in the resistance states, and describe how a pseudo-analog programming operation can be used for trimming ON-resistance values. Finally, we discuss how different memory initialization and programming approaches affect the reliability of an associative search.

Present a low power, miniaturized biomedical sensor node featuring electro-, seismo-and gyrocardiography. Measurement session can be set up and controlled over Bluetooth Low Energy interface. Acquired raw or preprocessed sensor data can be stored locally to the microSD memory card. To the best of the authors' knowledge, the presented device is the smallest reported to enable heart monitoring from the electrical and mechanical (with six degrees of freedom) viewpoint. The average power consumption of the device is less than 15mW, enabling continuous acquisition of high quality data of more than 60 hours with the used 250mAh Lithium-Polymer battery.

In this paper, a novel method to detect atrial fibrillation (AFib) from a seismocardiogram (SCG) is presented. The proposed method is based on linear classification of the spectral entropy and a heart rate variability index computed from the SCG. The performance of the developed algorithm is demonstrated on data gathered from 13 patients in clinical setting. After motion artifact removal, in total 119 min of AFib data and 126 min of sinus rhythm data were considered for automated AFib detection. No other arrhythmias were considered in this study. The proposed algorithm requires no direct heartbeat peak detection from the SCG data, which makes it tolerant against interpersonal variations in the SCG morphology, and noise. Furthermore, the proposed method relies solely on the SCG and needs no complementary electrocardiography to be functional. For the considered data, the detection method performs well even on relatively low quality SCG signals. Using a majority voting scheme that takes five randomly selected segments from a signal and classifies these segments using the proposed algorithm, we obtained an average true positive rate of [Formula: see text] and an average true negative rate of [Formula: see text] for detecting AFib in leave-one-out cross-validation. This paper facilitates adoption of microelectromechanical sensor based heart monitoring devices for arrhythmia detection.

Summary form only given. The Von Neumann bottleneck originates from the low bandwidth between processing and memory. One paradigm that could ease the bottleneck is Computing-in-Memory (CiM), where the same elements store logic values and perform logical operations on them in the same physical location. Here, presented are implementations of the K-means clustering algorithm on a Memristive Logic Array-based CiM implementation and a Machine Learning specific Transport-Triggered Architecture (TTA) processor implemented on 28nm FDSOI technology and operating at 0.35V. While running K-means, the Memristive CiM is 5,7 times faster and uses 2,3 times less energy than the TTA processor. However, the average power consumption of the MLA is 2,5 times the power of the TTA.

The primary aim of this work is to provide new tools for machine learning and reasoning within a framework of computing with holistic data representations. Specifically, we demonstrate recursive construction of mappings and functions in high-dimensional computing with random vectors - a connectionist computing model which provides benefits similar to neural networks, but allows compositional learning. The computational operations considered in this work are applicable in learning by generalizing from small sets of example data. We demonstrate their use by constructing a simple reasoning model which learns modulo 10 addition and subtraction from a minimal set of examples. Finally, we give examples on how the presented computational operations can be used to compose and manipulate more complex structures in computing with high-dimensional random vectors.

We describe how an analog associative memory architecture can be used to infer time-variant states of a hidden Markov model (HMM), demonstrating computation of forward probabilities, backward probabilities, smoothing, and the Viterbi algorithm. This type of computing is well suited for implementation in array computing architectures, and the necessary elementary computations have been demonstrated in previous work. We consider the effect of limited accuracy in storage and computing elements on the inference reliability, and demonstrate that although the computation is iterative, reliable operation is not significantly affected by error accumulation.

Distributed associative memory architectures store data in multiple locations redundantly, and are thus robust to circuit irregularities and noise. In this paper we explain ways to store the occurrence statistics of vectors in a distributed memory. Sparse data vectors are used to maximize vector capacity, and binding of sparse vectors is used to combine elementary symbols into symbols that represent larger entities. The use of such statistics is demonstrated with an on-line learning example that uses redundancy reduction. We show that occurrence statistics can be represented with distributed Willshaw-type associative memories sing hardware counters, as well as symbolically using two-bit memory cells.

In this paper we present a CMOS implementation of a 512×512-cell Associative Content Addressable Memory (ACAM) in 180 nm CMOS. The memory can be operated either as an associative CAM or it can be configured into a Willshaw memory for operating with sparse data. The vector matching operation can use a tunable hit threshold or the strongest hit can be selected with a winner-take-all (WTA) network. Built-in row and column circuitry can perform logic operations on the contents of the row and column memories. The operation of the circuit is verified experimentally with an example on computing with random vectors.

In this work we consider the implementation of nondeterministic finite automata in autoassociative memory, and demonstrate mapping and operating such automata in an associative content-addressable/Willshaw-type memory circuit presented in a companion paper. This topic is relevant in the broader scope of in-memory computing, and offers a simple, flexible, and computationally efficient way of implementing nondeterministic finite automata using existing general-purpose associative memory hardware.

We show a Field-Programmable Analog Array complemented with post-processed memristors (FPAA/memristor hybrid circuit), and present it as a platform for analog signal processing. The FPAA is fabricated on CMOS and uses floating-gate transistors (FGT) to realize programmable wiring fabrics and analog computing resources. The memristors, post-processed on top of the FPAA, are analog, which means that their conductance can be programmed in a continuous fashion. We highlight the key differences between FGTs and memristors, and discuss how analog signal processing tasks could be divided between them. Experimental results of the FPAA-memristor hybrid circuit are presented.

Associative memories, in contrast to conventional address-based memories, are inherently fault-tolerant and allow retrieval of data based on partial search information. This paper considers the possibility of implementing large-scale associative memories through memristive devices jointly with CMOS circuitry. An advantage of a memristive associative memory is that the memory elements are located physically above the CMOS layer, which yields more die area for the processing elements realized in CMOS. This allows for high-capacity memories even while using an older CMOS technology, as the capacity of the memory depends more on the feature size of the memristive crossbar than on that of the CMOS components. In this paper, we propose the memristive implementations, and present simulations and error analysis of the autoassociative content-addressable memory, the Willshaw memory, and the sparse distributed memory. Furthermore, we present a CMOS cell that can be used to implement the proposed memory architectures.

This paper describes how memristors, together with CMOS transistors (CMOS-memristor hybrids), could be used for analog arithmetic within cellular (locally connected, regular) computing arrays, i.e., cellular nanoscale networks (CNN). Elementary analog programming of memristors and copying memristance values are described. Also, we show how memristors could be used for addition, subtraction, multiplication and division. Furthermore, we demonstrate how a local memristive computing unit could be mapped into a CNN cell. Relevant memristor models are shown and key simulations are presented.

We propose three new synthesis methods for memristive implication logic and compare these with each other and with a basic method which was originally proposed in [5]. The results show that by using complementary representation of variables and multi-input operation, the lengths of computational sequences required for computing a given Boolean function are significantly reduced; for the three-input parity function this reduction is approximately 85 percent compared to the basic method.

We determine an explicit procedure for representing any Boolean expression in a recursive form which can be realized using memristive devices, and demonstrate how the truth value of any Boolean expression can be determined using no more than two computing memristive devices. We present an algorithm which can be used to significantly reduce the number of implications required for representing a specific Boolean expression, and consider device-specific benefits in terms of reducing the lengths of computational sequences.

We describe a generic exponential model with four parameters for thin-film memristive devices. This model is used to analyze the time dependency of the threshold voltage which defines the transition between non-programming and programming phases of the device. A relationship between timescale of operation and threshold voltage is derived. Furthermore, self-terminating programming is considered using the results of this analysis. Finally, the effect of parameter variations on the threshold voltage is analyzed.

This paper describes a cellular nanoscale network cell structure that is aimed to be built as a CMOS-nanomemristor hybrid. The processing cell uses memristors as ON-OFF programmable synapses, local logic and memory. Local logic is based on memristor computations using material implication. Only 15 CMOS transistors per cell are used, independent of the size of the neighborhood, since memristors are used as synapses. Also, space-dependent templates (weight matrices) are possible at no extra hardware cost. The operation of the cell is described and simulation results are shown to illustrate the operation.

In this paper, a novel approach to computing arbitrary Boolean functions using a binary-state cellular neural/nonlinear/nanoscale network (CNN) architecture with local static memory is presented. We define explicitly how to map a given Boolean function and its input values to the cells of a specific type of binary CNN, and the global rules used to perform parallel calculations. Each of the computation steps can be performed asynchronously. Additionally, the total CNN area is readily split into subsections, each of which perform individual computations of different Boolean functions. The main benefits of our approach are simple implementation of arbitrary Boolean functions, built-in parallelism both in local and global scale of the computation and the possibility for asynchronous operation.