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Sam D. Huynh

dblp:08/2828 · DBLP profile ↗
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5ranked-venue papers
3as first author
0since 2021 · last 1999
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 5 · 3 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test
analog circuit testing
0.011999
Test set selection for structural faults in analog IC's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999
Electronic design automation
hardware verification and test
0.011999
Test set selection for structural faults in analog IC's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999
Electronic design automation › hardware test
test selection
0.011999
Test set selection for structural faults in analog IC's · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1999

Methods — techniques the papers use, named apart from their topics

numerical optimization · 0.0monte carlo simulation · 0.0linear sensitivity analysis · 0.0covering problem · 0.0
YearPublicationVenuePosition
1999 Efficient Test Set Design for Analog and Mixed-Signal Circuits and Systems
abstract
A quick literature survey revealed that many researchers have and continue to work on automatic test pattern generation for analog and mixed-signal circuits and systems, however, very few if any have addressed the problem of test set size. This paper presents a novel test set compaction algorithm which takes a generated test set and maximally reduces the number of test vectors required while maximizing the fault coverage. Results show that 58.33% reduction can be achieved. Smaller test set implies lower total test time and long test times have been identified as one of the bottlenecks in analog and mixed-signal test.
Sam D. Huynh, Jinyan Zhang, Seongwon Kim, Giri Devarayanadurg, Mani Soma
Asian Test Symposium1
1999 A Test Point Insertion Algorithm for Mixed-Signal Circuits
abstract
This paper presents an algorithm based on testability measurement for test point insertion of mixed-signal circuits. Two transfer function models compatible with analog models are proposed: one is for digital devices and the other is for A/D interface components. An industry power supply circuit and a common A/D converter circuit are used to validate our approaches.
Jinyan Zhang, Sam D. Huynh, Mani Soma
VTS2
1999 Test set selection for structural faults in analog IC's
abstract
In this paper, we present methods for constructing optimal tests to detect structural faults in analog integrated circuits in the presence of process variation. The analog test determination problem is formulated as selecting an optimal subset from an initial large set of tests with optimality criteria defined in terms of fault coverage and fault separation on a given fault set. The process variation may be represented either deterministically by box constraints or statistically as random variables. Each of these representations require different methods for computing the detectabilities. In the deterministic case, the detectability measures are computed by a combination of analytical and numerical optimization techniques. Such an approach helps reduce the number of simulations by up to three times over traditional Monte Carlo methods. This approach produces more compact test sets compared to a linear sensitivity analysis while being closer in accuracy to the Monte Carlo method. In the statistical case, the detectability measures are computed as separation distances between the good and faulty distributions. These distributions represented nonparametrically are generated by traditional Monte Carlo techniques. Once the deterministic or statistical detectabilities are computed for the entire test set, a test compaction step is performed which is a covering problem. On solving this covering problem eve get a test set with optimal fault coverage and fault separation.
Giri Devarayanadurg, Mani Soma, Prashant Goteti, Sam D. Huynh
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.4
1998 Dynamic Test Set Generation for Analog Circuits and Systems
abstract
In this paper, we present an approach to construct a set of dynamic test signals for analog circuits and systems. Testability transfer factors are introduced and we use them as the basis to construct an efficient test set. Fault detectability and fault coverage are defined. Two circuits from the suite of analog and mixed-signal circuits are used to evaluate our approach. The fault coverage is 100% for both circuits studied. The approach presented may be used to construct inputs signals for the selection of an external stimulus applied through an arbitrary waveform generator.
Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang
Asian Test Symposium1
1998 Testability analysis and multi-frequency ATPG for analog circuits and systems
abstract
Fast and efficient test generation techniques are key to reducing the current high cost of testing analog circuits. A new multi-frequency test generation technique for detecting catastrophic failures in this class of circuits is presented. Testability transfer factors are introduced and we use them to construct an efficient test set for analog circuits. Fault detectability and fault coverage are also defined. Two circuits from the suite [4] of analog and mixed-signal benchmark circuits are used to validate our approach.
Sam D. Huynh, Seongwon Kim, Mani Soma, Jinyan Zhang
ICCAD1