In this paper, we investigate the differential and boomerang properties of a class of binomialFr,u(x) =xr(1 +uχ(x)) over the finite field Fpn, wherer=pn+1/4 ,pn≡ 3 (mod 4), and χ(x) =xpn−1/2 is the quadratic character in Fpn. We show thatFr,±1is locally-PN with boomerang uniformity 0 whenpn≡ 3 (mod 8). To the best of our knowledge, it is the second known non-PN function class with boomerang uniformity 0, and the first such example over odd characteristic fields withp> 3. Moreover, we show thatFr,±1is locally-APN with boomerang uniformity at most 2 whenpn≡ 7 (mod 8). We also provide complete classifications of the differential and boomerang spectra ofFr,±1. Furthermore, we thoroughly investigate the differential uniformity ofFr,uforu∈ F∗pn\{±1}.

The study of Boolean functions with low $c$-differential uniformity has become recently an important topic of research. However, in odd characteristic case, there are not many results on the ($c$-)differential uniformity of functions that are not power functions. In this paper, we investigate the $c$-differential uniformity of the swapped inverse functions in odd characteristic, and show that their $c$-differential uniformities are at most 6 except for some special case.

We present an r-th root extraction algorithm over a finite field Fq. Our algorithm precomputes a primitive rs-th root of unity ξ where s is the largest positive integer satisfying rs|q -1, and is applicable for the cases when s is small. The proposed algorithm requires one exponentiation for the r-th root computation and is favorably compared to the existing algorithms.

A novel portable hardware architecture of the Elliptic Curve Method of factoring, designed and optimized for application in the relation collection step of the Number Field Sieve, is described and analyzed. A comparison with an earlier proof-of-concept design by Pelzl et al. has been performed, and a substantial improvement has been demonstrated in terms of both the execution time and the area-time product. The ECM architecture has been ported across five different families of FPGA devices in order to select the family with the best performance to cost ratio. A timing comparison with the highly optimized software implementation, GMP-ECM, has been performed. Our results indicate that low-cost families of FPGAs, such as Spartan-3 and Spartan-3E, offer at least an order of magnitude improvement over the same generation of microprocessors in terms of the performance to cost ratio, without the use of embedded FPGA resources, such as embedded multipliers.

Tate-pairing-based cryptosystems, because of their ability to be used in multiparty identity-based key management schemes, have recently emerged as an alternative to traditional public key cryptosystems. Due to the inherent parallelism of the existing pairing algorithms, high performance can be achieved via hardware realizations. Three schemes for Tate pairing computations have been proposed in the literature: cubic elliptic, binary elliptic, and binary hyperelliptic. In this paper, we propose a new FPGA-based architecture of the Tate-pairing-based computation over binary fields. Even though our field sizes are larger than in the architectures based on cubic elliptic curves or binary hyperelliptic curves with the same security strength, nevertheless fewer multiplications in the underlying field need to be performed. As a result, the computational latency for a pairing computation has been reduced, and our implementation runs 2-20 times faster than the equivalent implementations of other pairing-based schemes at the same level of security strength. Furthermore, we ported our pairing designs for eight field sizes ranging from 239 to 557 bits to the reconfigurable computer, SGI Altix 4700 supported by Silicon Graphics, Inc., and performance and cost are demonstrated.

Tate pairing based cryptosystems have recently emerged as an alternative to traditional public key cryptosystems because of their ability to be used in multi-party identity-based key management schemes. Due to the inherent parallelism of the existing pairing algorithms, high performance can be achieved via hardware realizations. Three schemes for Tate pairing computations have been proposed in the literature: cubic elliptic, binary elliptic, and binary hyperelliptic. For our implementation we have chosen the binary elliptic case because of the simple underlying algorithms and efficient binary arithmetic. In this paper, we propose a new FPGA-based architecture of the Tate pairing-based computation over the binary fields F2239and F2283. Even though our field sizes are larger than in the architectures based on cubic elliptic curves or binary hyperelliptic curves with the same security strength, nevertheless fewer multiplications in the underlying field need to performed. As a result, the computational latency for a pairing computation has been reduced, and our implementation runs 10-to-20 times faster than the equivalent implementations of other pairing-based schemes at the same level of security strength. At the same time, an improvement in the product of latency by area by a factor between 12 and 46 for an equivalent type of implementation has been achieved

This paper presents a new digit-serial systolic multiplier over GF(2m) for cryptographic applications. When input data come in continuously, the proposed array produces multiplication results at a rate of one every [m/D] + 2 clock cycles, where D is the selected digit size. Since the inner structure of the proposed array is tree-type, critical path increases logarithmically proportional to D. Therefore, the computation delay of the proposed architecture is significantly less than previously proposed digit-serial systolic multipliers whose critical path increases proportional to D. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementations.

In this paper, an efficient digit-serial systolic array is proposed for multiplication in finite field GF(2/sup m/) using the standard basis representation. From the least significant bit first multiplication algorithm, we obtain a new dependence graph and design an efficient digit-serial systolic multiplier. If input data come in continuously, the proposed array can produce multiplication results at a rate of one every /spl lceil/m/L/spl rceil/ clock cycles, where L is the selected digit size. Analysis shows that the computational delay time of the proposed architecture is significantly less than the previously proposed digit-serial systolic multiplier. Furthermore, since the new architecture has the features of regularity, modularity, and unidirectional data flow, it is well suited to VLSI implementation.

Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF(2/sup m/), which has a low hardware complexity and a low latency. We show that our multiplier has a latency m+1 and the basic cell of our circuit design needs 5 latches (flip-flops). On the other hand, most of other multipliers of the same type have latency 3m and the basic cell of each multiplier needs 7 latches. Comparing the gates areas in each basic cell, we find that the hardware complexity of our multiplier is 25 percent reduced from the multipliers with 7 latches.

The FCM algorithm is an essential tool for the fuzzy classification. But it suffers vague decision diversity due to the heavy dependence upon the initial randomization. To provide less vague decision strategy we suggest a modified FCM algorithm that uses multiple randomizations of the membership functions. The algorithm inherently provides the parallelism and implied stochastic annealing of the convergence trajectory. The strategy to switch among multiple prototypes during each simulation step is the "majority voting" in nature. The algorithm naturally provides the "averaged rate of convergence" and a convincing decision measure to accept a "more suitable" class among huge set of all legitimate classifications. The contributions are 1) the MV FCM algorithm, 2) the sketch of the convergence analysis.