Frame-based visual-inertial odometry (VIO) can be significantly enhanced by integrating event cameras, particularly in high-speed motion and high-dynamic-range (HDR) scenarios. However, existing VIO frameworks often process event and frame-based data simultaneously, introducing unnecessary computational overhead. Additionally, tracking handcrafted features on event streams typically requires extensive parameter tuning and lacks robustness against noise. To address these limitations, we propose Hybrid-EVIO, a method that effectively fuses event data, standard frames, and inertial measurement unit (IMU) measurements. Hybrid-EVIO consists of a hybrid visual front-end and a sliding-window-based back-end. The front-end combines traditional and learning-based techniques in a scene-adaptive manner: features are tracked using either conventional methods on frames or a learned sparse optical flow network on asynchronous events, depending on the imaging quality. IMU measurements are further utilized to construct epipolar constraints, prefiltering extreme outliers before Random Sample Consensus and thereby improving pose estimation accuracy. Finally, a tightly coupled, graph-based optimization framework integrates three sensor modalities for high-precision state estimation. We evaluate the proposed method on multiple representative and challenging public datasets. Our approach outperforms state-of-the-art methods, reducing trajectory errors by up to 34% in the best case. Our trajectories and evaluation code are publicly available at https://github.com/sssxxxkkkk/hybrid EVIO.

Automatic registration of optical and synthetic aperture radar (SAR) remote sensing images has been extensively researched for decades. However, fast and robust multimodal image registration is still a challenge due to the significant region differences in many remote sensing scenarios (e.g. city and sea region coexist in single harbor imaging). To address this problem, this paper proposes a novel optical-to-SAR registration method called FED-HOPC, which integrates the fast Fourier transform (FFT) and weighted edge density (WED) map into the histogram of oriented phase congruency (HOPC) based registration framework. FFT is used to accelerate the 3D normalized cross-correlation (NCC) for the coarse matching. WED map is employed to detect adaptive block-based interest points, which are used to build region aware HOPC descriptors for the following fine registration. To evaluate the performance of FED-HOPC, extensive experiments on four optical-to-SAR registration datasets are conducted. The results demonstrate that FED-HOPC effectively register optical-to-SAR images with significant region differences and outperforms several state-of-the-art methods, including HOPC, MIND, MIRD, and CFOG.

Both text detection and structured data extraction are imperative in an optical character recognition (OCR) processing pipeline. Text detection, especially for indistinct, diverse, multi-language text regions, is one of the most challenging tasks in computer vision and has attracted increasing attention recently. Moreover, although there are some studies in data mining related to structured data extraction, it has not received its deserved attention as one of important steps in OCR. The previous methods for structural data extraction, including layout template-based, rule-based, and natural language processing (NLP)-based methods, usually leads to either inaccurate results or complex modules. In this paper, we integrate text detection and structured data extraction into a unified deep learning-based Image Text Extraction (ITE) scheme. Our ITE is an end-to-end trainable model and able to handle multi-scale and multi-lingual text in a single process. Experiments on large-scale real-world passport and medical receipt datasets have demonstrated the superiority of the proposed method in terms of both effectiveness and efficiency.

SRAM arrays using differential sensing (DS) and single-ended sensing (SE) are designed and fabricated in a test chip and their power and performance behaviors are studied in this paper. Sense amplifier offset (DC condition), which is one of the main criterion to determine the required bit-line differential, is measured. A novel SE scheme is proposed to overcome the delay degradation due to large bit line leakage in scaled technology. With marginal switching power savings, the SE array is 56% slower than the DS array in 90 nm technology with a single high-Vt at 350 mV. The difference narrows down to 30% in low-Vt case. Using asymmetric cells, instead of symmetric cells, in single-ended large signal arrays improves delay by 3%, while the power consumption remains approximately the same.

This paper proposes a bus architecture called skewed repeater bus (SRB) for reducing on-chip interconnect energy in microprocessors. By introducing relative delay between neighboring bus lines, SRB reduces both average and worst-case coupling capacitance between those lines. SRB is compared to previously published techniques like delayed data bus (DDB) and delayed clock bus (DCB). Simulation results in 65-nm process show that bus energy reduction of 18% is achieved when SRB is applied to a real microprocessor example, versus 11% and 7% only for DDB and DCB; respectively.

We investigate trade-offs in microprocessor frequency and system power achievable for low temperature operation in scaled high leakage technologies by combining refrigeration with supply voltage selection, body bias, transistor sizing and shorter channel length. Reducing channel length provides better frequency and power improvement than forward body bias. When, the leakage power is more than 30 of chip power, combining refrigeration with enhancing technology by shorter channel length provides the best trade-off for power and frequency.

We describe various design automation solutions for design migration to a dual-Vt process technology. We include the results of a Lagrangian Relaxation based tool, iSTATS, and a heuristic iterative optimization flow. Joint dual-Vt allocation and sizing reduces total power by 10+% compared with Vt allocation alone, and by 25+% compared with pure sizing methods. The heuristic flow requires 5x larger computation runtime than iSTATS due to its iterative nature.

This paper compares different high-V/sub T/ and dual-V/sub T/ design choices for a large on-chip cache with single-ended sensing in a 0.13 /spl mu/m technology generation. The analysis shows that the best design is the one using a dual-V/sub T/ cell, with minimum channel length pass transistors, and low-V/sub T/ peripheral circuits. This dual-V/sub T/ circuit provides 20% performance gain with only 1.3/spl times/ larger active leakage power, and 2.4% larger cell area compared to the best design using high-V/sub T/ cells with nonminimum channel length pass transistors.

A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit is cross-talk, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified by HSPICE simulation on DOMINO gates. A tool is also developed to obtain static and dynamic noise-margins at various points in the circuit. Dynamic noise-margins are translated into maximum allowable coupling capacitances between the pairs of nets for precharge-evaluate logic circuits. An accurate estimate of dynamic noise-margin and coupling coefficient bounds will allow improvement of the circuits in terms of robustness.

The use of XOR gates has shown several advantages in modern circuit design, e.g. smaller representation size and better testability. In this paper we consider power consumption in XOR dominated circuits and compare such designs with traditional AND/OR logic. We investigate the suitability of using different delay models such as unit delay, fanout delay, and random delay in power estimation of XOR dominated logic. Due to different possible implementations of XOR gate, we model the XOR gate as a basic gate and a complex static CMOS gate, respectively. Power dissipation due to (charging and discharging) internal node capacitances is also considered.

Dual threshold technique has been proposed to reduce leakage power in low v oltage and low p o w er circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance.Mixed-Vth (MVT) static CMOS design technique allows dierent thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique.In this paper, a methodology for MVT CMOS circuit design is presented.Dierent MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistorlevel threshold assignment under performance constraints.Results indicate that MVT CMOS design technique can provide about 20% more leakage reduction compared to the corresponding gate-level dual threshold technique.

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

A new graph-based synthesis method for general Exclusive Sum-of-Product forms (ESOP) is presented in this paper. Previous research has largely concentrated on a class of ESOP's, the Canonical Restricted Fixed/Mixed Polarity Reed-Muller form, also known as Generalized Reed-Muller (GRM) form. However, for many functions, the minimum GRM can be much worse than the ESOP. We have defined a Shared Multiple Rooted XOR-based Decomposition Diagram (XORDD) to represent functions with multiple outputs. By iteratively applying transformations and reductions, we obtain a compact XORDD which gives a minimized ESOP. Our method can synthesize larger circuits than previously possible. The compact ESOP representation provides a form that is easier to synthesize for XOR heavy multilevel circuit, such as arithmetic functions. The method successfully minimized large functions with multiple outputs. Results are also compared to the minimized SOP's obtained from ESPRESSO. Experimental results show that for many circuits ESOP's have considerably more compact form than SOP's.

In this paper, weintroduce a Shared Multiple Rooted XORbased Decomposition Diagram #XORDD# to represent functions with multiple outputs. Based on the XORDD representation, we develop a synthesis algorithm for general Exclusive Sum-of-Product forms #ESOP#. By iteratively applying transformations and reductions, we obtain a compact XORDD which gives a minimized ESOP. Our method can synthesize larger circuits than previously possible. The compact ESOP representation provides a form that is easier to synthesize for XOR heavy multi-level circuit, such as arithmetic functions. Wehave applied our synthesis techniques to a large set of benchmark circuits in both PLA and combinational formats. Results of the minimized ESOP forms obtained from our synthesis algorithm are also compared to the SOP forms generated by ESPRESSO. Among the 74 circuits wehave experimented with, the minimized ESOP's have fewer product terms than those of SOP's in 39 circuits. 1 INTRODUCTION In many applications, the AN...

Article Quasi-static energy recovery logic and supply-clock generation circuits Share on Authors: Yibin Ye School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Kaushik Roy School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN School of Electrical and Computer Engineering, Purdue University, West Lafayette, INView Profile , Georgios I. Stamoulis Low Power Design Technology, Intel Corp., Santa Clara, CA Low Power Design Technology, Intel Corp., Santa Clara, CAView Profile Authors Info & Claims ISLPED '97: Proceedings of the 1997 international symposium on Low power electronics and designAugust 1997 Pages 96–99https://doi.org/10.1145/263272.263293Online:01 August 1997Publication History 7citation262DownloadsMetricsTotal Citations7Total Downloads262Last 12 Months2Last 6 weeks1 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access