This paper presents a power-linear regulator (PLR) using a voltage-squaring feedback loop designed for linear thermo-optic tuning. Nonlinear phase tuning occurs when conventional digital-to-analog converters (DACs) or low-dropout regulators (LDOs) are used to drive the thermo-optic phase shifter since the introduced phase change is proportional to the square of the voltage. The nonlinear phase tuning introduces the distortion and non-uniform resolution which degrades the system performance. We propose a PLR to achieve linear thermo-optic phase tuning, where the phase change is proportional to the input voltage. By adopting a voltage-squaring feedback loop, the output voltage is proportional to the square-root of the input voltage under fixed resistive heater and a linear mapping between the input voltage and phase change is established. This design is fabricated in a standard CMOS 65 nm process with an active area of 0.014 mm2. Under 2.5 V supply voltage, the proposed design achieves an input range of$0\sim 1$V and corresponding output range of$0\sim 2$V. The maximum delivered power is up to 40 mW while driving a$100~\Omega $load. The measured power linearity error is$3.5~\%$. Additionally, the design demonstrates rapid transient behavior under a$100~\Omega $load, with$0.2~\mu $s rise time and$0.7~\mu $s fall time between 0 mW output power and 40 mW output power. The line regulation is 6 mV/V under$100~\Omega $load. To the best of our knowledge, it is the first PLR demonstrated in the literature.

This paper presents general SPICE photonic models for closed-loop electronic-photonic co-simulation. SPICE models are originally intended for electronic devices, which have significantly different physics compared to photonic devices. Most existing SPICE photonic models are specialized and fail to capture important features like multi-dimensional signals. It remains a key challenge to represent general photonic devices using SPICE models that include their essential features. To address the above challenge, we separate the signal meaning from its numerical result and adopt a numerically-equivalent approach to construct photonic models using native SPICE primitives. And the designer is left to interpret the meaning of the numerically-equivalent electronic signals, such as wavelength and polarization. Our models encompass the features of existing SPICE models, including wavelength dependence and bi-directional transmission, as well as new features beyond those. Specifically, polarization, optical Kerr effect, two-photon absorption, free carrier absorption, and free carrier dispersion are included in our SPICE models. Closed-loop polarization simulation is realized for the first time. We can quickly achieve frequency-domain simulation by DC sweep instead of stepped frequency transient simulations or frequency chirp-based methods. Our SPICE photonic models show excellent agreement with the simulation results of Verilog-A models and Lumerical models. Our SPICE photonic models are more efficient in co-simulation with SPICE electronic models than Verilog-A photonic models due to less compiling time and better compatibility. Our general models make the circuit design of electronics-photonics convergence (EPC) as convenient as that of traditional integrated circuits, paving the way for the circuit-level convergence of electronics and photonics.

This paper presents a four-channel time-division-multiplexing clocked-analog low-dropout regulator (TDM CLDO) using a novel current Miller compensation with a degenerated resistor (CMDR) block for thermo-optic tuning in silicon photonics. Previous TDM LDOs require a dedicated compensation capacitor for each channel because, during controller switching, one node of the compensation capacitor experiences large voltage variations that hinder multiplexing the capacitor. A novel CMDR block that is disconnected from voltage nodes with large variations is proposed to multiplex the compensation capacitor. Furthermore, Gray-code addressing technique is adopted to reduce the crosstalk between four channels caused by clock timing errors. Implemented in a 65 nm CMOS process, this design has a total chip area of 0.0047 mm2, which is 55% smaller than the conventional solution with four identical LDOs and consumes a quiescent current of$3.1 \mathrm {\mu }\text{A}$per channel. Measured results show that the presented four-channel TDM CLDO can simultaneously track four 1 Vpp sinusoidal signals up to 200 kHz. To our knowledge, this is the first time that a compensation capacitor is shared between different LDO channels.

This article proposes a high-efficiency all-nMOS bidirectional charge pump (CP) cell and constructs a CP-based high-voltage (HV) pulse driver based on it. Double-diode substrate isolation (DDSI) can extend the maximum supported voltage in a bulk CMOS process, but it requires an all-nMOS implementation of CP cells. Existing all-nMOS CPs either do not support the bidirectional charge transfer required for HV pulse drivers, or achieve it with additional penalties such as reversion charge loss and overstress on transistors. The proposed all-nMOS CP with novel gate voltage control strategies is the first one reported in the literature that can support the bidirectional charge transfer required for HV pulse drivers without suffering from reversion loss and threshold voltage loss or causing overstress on transistors. A ten-stage CP-based HV pulse driver is implemented in a 65-nm CMOS process utilizing this cell. Postlayout simulation results demonstrate that it can reliably generate 20-V HV pulses from a 2.5 V supply for a 15 pF // 200 k$\Omega $load at 55 kHz. The driver exhibits a peak power efficiency of 46.4% and occupies an area of 0.262 mm2.

A novel switching-linear hybrid dynamic regulator architecture with dual-supply low dropout regulators (LDOs) is presented in this paper. This architecture leverages the intrinsic dual supplies to extend the operating range of the LDOs. Furthermore, it increases the thermo-optic tuning efficiency by reducing the LDO dropout voltage through dynamic supply modulation. This architecture is suitable for large-scale thermo-optic tuning in silicon photonics. The efficiency improvement is particularly effective when tracking signals of several adjacent channels are close to each other, e.g., wavelength tuning of a microring array. The principle of this architecture is general and can be implemented using different switching converters and LDOs. A specific design with extensive post-layout simulation results is used to verify the effectiveness of our architecture. Implemented in a 130 nm CMOS process, this design can simultaneously regulate eight output channels with an output swing of 0.8$\text V_{\text {pp}}$. Its peak efficiency when driving 100$\Omega $loads is 92% at 1 V output, and the dynamic efficiency is around 86% when tracking 50 kHz sinusoidal signals. To the best of our knowledge, this is the first time that dynamic supply modulation has been applied to multi-channel thermo-optic tuning of silicon photonic devices.

A 57.2-Gb/s four-level pulse-amplitude modulation (PAM4) driver for silicon photonic Mach-Zehnder modulator (MZM) is presented. The driver is designed in a 45-nm RF-SOI CMOS technology and consists of a pre-driver and an outputdriver. The pre-driver is made up with scaled, cascaded single- ended CMOS inverter transimpedance amplifiers with inductive and resistive feedback and interstage series inductive peaking. The output-driver adapts the structure of series-stacked cascoded CMOS inverter to overcome the breakdown voltage (BV) limit of transistors in advance technologies while getting high differential voltage swing >4 Vpp for MZM. The MZM is configured as an optical digital-analog converter (ODAC) and consists of a 1.1 mm LSB segment and a 1.9 mm MSB segment. The post-layout simulation results show that 5.6-Vpp differential swing, 9.1 dB extinction ratio (ER) and 95.2% ratio of level mismatch (RLM) at 28.6-GBaud (57.2-Gb/s) with a total power consumption of 750 mW are realized. Furthermore, a larger ER can be obtained by increasing the supply voltage. This work achieves an optimized tradeoff between power consumption, data rate, output swing, chip area and extinction ratio.

This paper presents a time-division-multiplexed (TDM) clocked-analog low-dropout regulator (CLDO) that shares one controller between multiple output channels. Clocked-analog operation is introduced to create idle periods that enable the shared controller to independently regulate different output channels through time-division multiplexing. Furthermore, an asynchronous transient enhancing technique is presented. Thanks to the controller sharing, the TDM CLDO is more area-efficient than conventional designs for supplying multiple outputs, especially when power stages and on-chip loads are small. To verify the effectiveness of the TDM CLDO, a dual-channel version is fabricated in a 130 nm CMOS process. Measurement results show that it can independently track two 100 kHz 0.3 Vppsinusoidal signals with 4 mV average output error at 100 Ω load and 6 MHz clock frequency. For load transient responses, it can independently regulate two output channels to 1.05 V and 0.95 V with 41 mV/88 mV and 67 mV/39 mV overshoot/undershoot when both channels experience 5 mA current steps at 1.2 Vdd. To the best of our knowledge, this is the first time that hardware sharing is implemented for continuous closed-loop systems.

This paper presents a time-division-multiplexing (TDM) scheme for simultaneous wavelength locking of multiple silicon micro-rings by exploiting the speed mismatch between the heater and the controller. This scheme could reduce the overall chip size significantly without reducing the wavelength lock speed. It also avoids cross-channel coupling using the least number of ADCs and DACs. The simplest TDM scheme involving two micro-rings is experimentally verified using board-level circuits. Theoretically, this approach can be scaled to even hundreds of micro-rings, pointing out a way towards large-scale integrated optoelectronics, which is required by many important applications, such as wavelength division multiplexing for chip-to-chip optical I/O.

In this paper, we study the stability conditions for hybrid supply modulators (HSMs). We investigate the limitations of the Nyquist stability criterion, the standard technique of evaluating the stability of a linear time-invariant (LTI) system, when applied to HSMs, and demonstrate that it cannot assess the stability of two recent HSMs. To overcome these limitations, a general large-signal stability condition is suggested, which can be regarded as a natural extension of the stability condition used for hysteretic-controlled HSMs. It successfully explains the stability of these two recent HSMs. Based on the new stability condition, we propose two control methods for HSMs that couple the input signal to the switching loop directly, and verify their stability by timedomain simulation results. The proposed stability condition opens door for constructing new HSMs.

This paper presents a generic model that links the compensation techniques used in two-stage amplifiers to the structures of three-stage amplifiers. Many previous designs can be derived from this model, and new three-stage amplifiers can potentially be constructed. A novel three-stage amplifier based on this generic model is proposed. Simulation results show that the proposed design outperforms many recent designs.

In this work, an output-capacitor-free (OCF) low-dropout regulator (LDR) employing fully differential input stage is proposed. By using a fully differential input stage, the proposed OCF LDR is able to improve the transient responses without the help of any additional transient boosting circuitry. This design is stabilized with a 0.37pF compensation capacitor. It is able to provide a maximum load current of 100mA at 0.7V to 1.2V supply with less than 200mV dropout voltage. Implemented in 0.13μm CMOS technology, it consumes a quiescent current of 4μA and occupies an active area of 0.0132mm2.