This paper presents a design approach for fast- locking and low jitter self-biased phase-locked loop (PLL). The charge-pump current injection technology with minimum area overhead is adopted to accelerate the loop equilibrium capture process without sacrificing the jitter performance. A start-up circuit is proposed in order to shorten the initial ramping up interval of the voltage-controlled oscillator (VCO), which will also help in reducing the lock-in time. A proportional coefficient is introduced in designing self-biased PLLs, which provides more flexibility regarding practical circuits design. The proposed fast- locking self-biased PLL is designed in a TSMC 28nm CMOS process with a supply voltage of 0.9 V. The simulation results show that the locking time is reduced by up to 85% for large division ratios and should not deteriorate the capture performance in small division ratios. Meanwhile, the system almost has no increase in area and the locking time is reduced from 24us to about 3us when operating at 6GHz.

The mitigation of single-event upset (SEU) in SRAM-based field-programmable gate array (FPGA) is increasingly important as utilization and demand for SRAM-based FPGA dramatically increased in radiation environments such as space. As D flip-flop (DFF) and memory [including block random-access memory (BRAM) and configuration random-access memory (CRAM)] are constituted as the key elements in an FPGA, it is fundamentally necessary to develop radiation hardening techniques targeted for enhanced reliability of DFF and memory. A novel SEU hardened memory design for FPGA is proposed with capabilities of multibit upset protection. We further developed two prototype FPGA chips, one with SEU and the other without SEU hardening for comparison. The FPGA chips are fabricated in a standard 0.13-$\mu \text{m}$CMOS process and have a volume of three million equivalent logic gates. In terms of SEU cross section, CRAM in the hardened FPGA design is about four orders of magnitude lower than in the unhardened FPGA design, while BRAM demonstrates a reduction by three orders of magnitude. On the conditions of linear energy transfer being up to 14 MeV$\cdot$cm2/mg, no SEU errors were observed from DFF in the hardened FPGA design.

In recent years, Convolutional Neural Networks (CNNs) have been used widely in many artificial intelligence (AI) related fields. Of many implementation platforms for CNNs, FPGA is regarded as an optimal platform because of its high power-efficiency and flexibility. Although various FPGA accelerators have been proposed to realize CNN, some of them are implemented by High-Level Synthesis such as in OpenCL. This may result in inefficiency in operation performance and resource utilization. Therefore, we propose to parameterize the RTL design at both algorithm and hardware implementation levels. Four types of parallelism are considered to model the parameterized design in terms of the input feature map, the output feature map, the layer and the convolution kernel. Meanwhile a library covering convolution layer, fully-connected layer, pooling layer, control module is established to cater for various CNN models. Further, an algorithm is proposed to find an optimal level of parallelism dedicated to limited resources. As a case study, four typical CNNs are implemented on Stratix III EP3SL110, taking up on-chip memory. Compared with some existing works using the automated design flow, the implementations obtained by the proposed approach have achieved up to 17.13× GOPS. To the best estimate, our design has also achieved 1.33× resource efficiency and 3.61× power efficiency.

Reconfigurable digital filter is being widely used in applications such as communication and signal processing. Its performance, power consumption, and logic resource utilization are the major factors to be taken into consideration when designing the filters. This paper proposes a concise canonic signed digit coefficient grouping method aiming at reducing the number of common subexpressions (CSs). Further, we statistically analyze every CS occurance for numerous sorts of the finite-impulse response (FIR) filters and obtain characterization of the distribution behavior for all the possible CS patterns in a 16-bit coefficient. Thus, a novel processing element structure is proposed to form a medium-grain array for computationally efficient realization of reconfigurable FIR filter. The experiment results suggest such design implementations typically achieve 21% reduction in silicon area, 20% decrease in power consumption, and 14% improvement in operation speed in comparison to other conventional FIR architectures.

In the last decade, progress in logic synthesis has brought about new advantageous circuit representations. These representations, such as And-Inverter Graphs in the ubiquitous open-source synthesizer ABC, have inspired new designs of Field Programmable Gate Arrays (FPGAs), which, instead of using Look-Up Tables (LUTs), mimic the topology of the circuit representation in the basic logic cells. More recent examples are Majority-Inverter Graphs, another uniform representation which has triggered considerable interest in synthesis and which naturally suggests new logic cells. Yet, in this paper we observe how naïvely adapting technology mapping solutions for classic LUT-based FPGAs to these new architectures incurs severe shortcomings. The key issue is that LUTs are inherently input-constrained (the logic function they implement is irrelevant) and have generally a single output; on the other hand, logic cells made of uniform networks of some fundamental logic function (e.g., And-Invert) are constrained in terms of logic depth and multiple outputs are an integral feature. We introduce novel and effective solutions to address these differences; the result is a highly versatile mapper—thus enabling further research in these new architectures—with a significantly better performance than what is described in literature for one such architecture. Specifically, when we compare with the state of the art on one sample architecture, we obtain a significant decrease in area (on average 18% over several benchmarks) while also improving slightly the critical path (a reduction of 3%).

This paper presents a low noise chopper-stabilized instrumentation amplifier (IA) for EEG recording. The current-reuse technology is adopted to reduce noise of the IA and the regulated cascode circuit is used to boost the open-loop gain of the amplifier. A ripple reduction loop (RRL) based on a novel output-resistance-tuning technology is proposed to reduce the intrinsic offset of the IA and reduce the output ripple of the chopper amplifier. Simulation results show the high-pass cutoff frequency of 0.15Hz, the input referred noise of 0.7μVRMS(BW=100Hz) and a NEF of 2.83. The attenuation to the chopping ripple is about 35dB with the novel output-resistance-tuning based RRL. The proposed IA achieves an average CMRR of 110dB, average PSRR of 105dB and average input-impedance of 1.5GΩ from Monte Carlo analysis. The overall IA consumes only 1.1μA current at a 1.2V supply.

This brief presents a fast-locking multiphase closed-loop delay-locked loop (DLL). The proposed DLL employs a novel rapid-tracking time-to-digital converter that spends only two clock cycles to generate fine codes. This greatly reduces the fine-locking time and hence the total locking time that goes down to eight input reference clock cycles, shortened by 80%-95% compared with previously reported closed-loop architectures. Fabricated in a 130-nm technology, the proposed DLL operates at 80-450 MHz. In addition, the measured rms and peak-to-peak jitters at 180 MHz are 2.3 and 10 ps, respectively.

A high-speed CMOS TSPC divide-by-16/17 dual modulus prescaler is proposed. The speed of the prescaler is improved in two aspects. First, by adopting a new pseudo divide-by-2/3 prescaler, the minimum working period is effectively reduced by half a NOR gate's delay. Second, by changing the connection of TSPC D-Flip-Flops, the minimum working period is further reduced by half an inverter's delay. Simulation results show that the maximum operating frequency of the proposed circuit is improved by ~40% compared with conventional circuit. Fabricated in 0.18-μm CMOS process, the proposed circuit is capable of operating up to 5.8 GHz. The power consumption is 2.6 mW at the maximum operating frequency under 1.6 V supply voltage.

And-Invert Cones (AICs) have been suggested as an alternative to the ubiquitous Look-Up Tables (LUTs) used in commercial FPGAs. The original article suggesting the new architecture made some untested assumptions on the circuitry needed to implement AIC architectures and did not develop completely the toolset necessary to assess comprehensively the idea. In this paper, we pick up the architecture that some of us proposed in the original AIC paper and try to implement it as thoroughly as we can afford. We build all components for the logic cluster at transistor level in a 40~nm technology as well as a LUT-based architecture inspired by Altera's Stratix~IV. We first determine that the characteristics of our LUT-based architecture are reasonably similar to those of the commercial counterpart. Then, we compare the AIC architecture to the baseline on a number of benchmarks, and we find a few difficulties that had been overlooked before. We thus explore other design possibilities around the original design point and show their detailed impact. Finally, we discuss how the very structure of current logic clusters seems not perfectly appropriate for getting the best out of AICs and conclude that, even though they are not confirmed as an immediate blessing today, AICs still offer rich research opportunities.

FPGA-based SoCs have been gaining great favors among traditional applications and expanding the application domains to some new areas. Reusing and sharing components is an attractive and pratical methodology for system designers to reduce the design complexity of the SoC architectures. Open source hardware has become an effective method of improving the design productivity. As the core functional component, processors affects the performance of SoC systems. This paper investigates existing open source processors, and gives an overview. From the points of usability and stability, the main features of open source processors are summarized. Following these features, some open source processors with high usability and stability are selected. These open source processors and existing vendor-provided soft processors are implemented on Stratix V and Virtex-7 FPGAs using corresponding EDA tools, Quart us n and ISE. The implementation results are compared and discussed.

Dual-output lookup tables (LUTs) are mainstream in the design of commercial FPGA products. A detailed exploration of architectural parameters of FPGAs based on dualoutput LUTs is presented. Different from traditional single-output LUT based architecture, “shared inputs” between the sub-LUTs is a new parameter specific to dual-output architecture. In this paper, we focus on the effect of ratio of shared inputs on the performance and area-efficiency. First, we study the required cluster inputs and derive a relationship between cluster inputs, LUT size and cluster size under different ratios of shared inputs. Secondly, our evaluation results show that a FPGA with 4-LUTs and a shared input ratio of two thirds is preferred for area-efficiency, while a large LUT size of 9 with no shared inputs achieves best performance. Finally, we determine that a LUT size of 4, a cluster size from 3 to 8, and a shared input ratio between 1/3 and 2/3, provide the best area-delay product for dual-output LUT based FPGAs.

An approach to estimate the performance of FPGA architectures is proposed based on semi-supervised model tree algorithm. The proposed approach avoids synthesizing, mapping, packing, placing and routing, which are essential steps in a traditional flow to obtain the performance of FPGA. Thus it is time efficient while the performance predicted maintains quite close to the result obtained through the traditional method (a tool flow called VTR). This can be utilized effectively during the early FPGA design stage to choose an optimal architecture under a certain metric. Comparisons are made between the performance obtained by the proposed approach and by VTR on a commercial 40nm technology. Results show that the proposed approach has MRE below 7.62% compared to VTR, and improves the time cost by thousands of times when utilized in architecture design space exploration.

In this paper we first examine the impact of FPGA size on overall performance and run-time of placement and routing in the context of cluster-based island-style FPGAs. Based on the observations, an FPGA placement algorithm, Min-Size, is introduced to alleviate the deterioration of performance and run-time of placement and routing when using a large FPGA to implement a circuit. We achieve this by allowing Min-Size to generate a more compact placement of logic, I/O and hard blocks. Our experimental results have shown a 3X and AX speedup in placement and routing run-time, a 38% and 41% reduction in wire length, and a 8% and 5% improvement in critical path delay when FPGA size increases 10 times.

A Field-Programmable Analog Array (FPAA) architecture designed for intelligent sensory application is presented, which consists of high performance and high flexible Configurable Analog Blocks (CABs). The CAB is developed to realize both continuous-time and discrete-time circuits for achieving optimal performance in different applications. In addition to employ coarse-grained reconfigurable CAB in FPAA, a fine-grained reconfigurable amplifier in the CAB is utilized to maximize programmability and flexibility. The precision of the analog processing is enhanced by employing fat-tree interconnection network topology to minimize the number of switches used in FPAA and using correlated double sampling (CDS) techniques to suppress the offset and noise. The FPAA is designed and implemented in SMIC 0.18μm CMOS process with a 3.3 V supply voltage. An instrumental amplifier and a capacitive sensor signal readout circuit are taken as application examples. The relative precision and dynamic range of the analog processing are 97.6% and 119dB respectively.

Physical block memory is one of the earliest hardened blocks in modern FPGAs. FPGA memory mapping utilizes memory blocks to construct user's logic memory designs. Previous mapping methods optimized for circuit area or power consumption. However, timing performance becomes more important for large and critical logic memory designs. In this work, a critical path delay model will be presented for the first time to estimate implementation performance during memory mapping. Experiment results showed that over 90% estimation errors by the model were within 10% and the average was only 3.5%. Based on the delay model, we proposed the first timing-constrained FPGA memory mapping algorithm. The algorithm generates memory configurations that meet the user's performance requirement. The algorithm also achieves optimal area/power subject to the user's timing constraint. The area or power optimum was validated with a commercial FPGA memory mapper.

Performance and power consumption are two important aspects of reconfigurable finite impulse response (FIR) filters. In this paper, a new reconfigurable FIR architecture named SCSD FIR is proposed. This proposed architecture has been synthesized in 0.13 μm technology with a precision of 16 bits. Design example shows that FIR with 551 taps achieves 21.3% area reduction and 19.0% power reduction compared with the most efficient existing architecture of FIRs. It also achieves an improvement of 13.1% in speed. Furthermore, these advantages are expanded as the taps of filters are increasing.

In an ultra low voltage hearing aid front-end system on chip, a novel Current Mode Feed-Forward Gain Control (CMFGC) technique is presented. Compared with the conventional automatic gain control (AGC), CMFGC significantly reduces the total harmonic distortion (THD) without worsening other performances by digitally controlling the passive resistor array. To attain the digital control codes according to extremely weak signal from the microphone, a novel high precision current mode rectifier is proposed. A prototype chip has been designed based on a 0.13μm standard CMOS process and tested with 0.8V supply voltage. The measurement results show that the THD of the system is between 0.02% and 0.06% at the output level of 500mVp-p. In addition, the typical input referred noise within the system's bandwidth is 4μVrmsand the typical power consumption of the complete system is 40μW.

A novel structure of CMOS low voltage bandgap reference, called "Subtracting BandGap Reference" (SBGR), is proposed. In this work, the extremely small temperature coefficient is obtained by subtracting two Complementary To Absolute Temperature (CTAT) currents with same temperature coefficient but different magnitude. The subtraction of two CTAT currents which have similar characteristics leads to low temperature coefficient. Simulation results show that the new SBGR circuit achieves a temperature coefficient three times lower than that of the conventional low voltage bandgap reference.

In this paper, a novel air-gap-based coaxial Through Silicon Via (TSV) was proposed for on-chip RF interconnect, to fill up the increasing bandwidth gap between the demand and supply according for the 2007 International Technology Roadmap for Semiconductors. Based on earlier work, the expressions of characteristic impedance, attenuation and bandwidth have been proposed. Consequently, we assume an 80 multi-core 3D Network-on-Chip (NoC) system with Binary Phase Shift Keying (BPSK) modulation, to evaluate energy per bit and area per Gbps of the proposed air-gap-based coaxial TSV. The result indicates that the energy dissipation and area consumption of the proposed one are 40~50% and 10% better than the conventional dielectric RF TSV.

In this paper, through-silicon via (TSV) array in the form of one signal and four grounds (1S4G) are proposed to achieve high-frequency vertical connectivity for various three dimensional (3D) IC applications. Self-test method is developed to detect the conductor open and insulator short defects of TSV by capacitive and resistive measuring. Further a recovery mechanism for such a TSV array is introduced to enhance the TSV reliability. Test results will be configured to the TSV chain circuits by the central control logic and be used to determine the connection jumping between signal and redundant TSVs. This way, the failure TSVs could be replaced by the redundant ones. Simulation results demonstrate that the self-test circuit and central control logic could detect and recover the broken TSVs correctly. Moreover, the efficiency and area cost of the recovery mechanism is discussed, and it turns out that in a typical case of 96 signal TSVs, the chip yield could reach 90% with TSV failure rate equal to 5%, in exchange for less than 4% area cost of self-test circuit in the whole TSV area.

In this paper, radio frequency (RF) through-silicon via (TSV) designs and models are proposed to achieve high-frequency vertical connectivity for three dimensional (3D) multi-core and heterogeneous ICs. Specifically, coaxial dielectric and novel air-gap-based TSVs are designed and simulated to reduce signal degradation during RF operations. The simulation results demonstrate that these RF TSVs can provide decay-tolerance frequencies two orders of magnitude higher than simple Cu-plug TSVs. The data rate and energy per bit of the RF TSVs are summarized, providing an important guideline for future 3D high-frequency TSV designs.

FPGA is an efficient reconfigurable IC platform and is playing an increasingly important role in the electronics prototype implementation. With the rapid development of semiconductor technology and nano-technology over the last decade, FPGA has entered into a Giga-scale era. In this paper, the current status and future directions of Giga-scale FPGAs are presented. Specifically, the emerging technology-based FPGAs such as asynchronous FPGA, 3-dimensional FPGA, memristor-based nanoFPGA, and embedding-module FPGA, are discussed to solve the current FPGA challenges of timing constringency, signal integrity and power issues. This survey article aims to provide a guideline to future FPGA development.

A low power continuous phase-switching multi-modulus prescaler is proposed, based on a so called “time borrowing” method. This novel phase-switching control strategy significantly reduces the delay of the phase-switching control loop so the multi-modulus prescaler can work with higher input frequencies and obtain the maximum modulus for a lower power supply. According to the measurement results, such a multi-modulus prescaler fabricated in a 0.35μm CMOS process divides the 2.4GHz input frequency by 48 up to 64 for a minimum power supply voltage of 2.5V. Its maximum power dissipation is only 4.85mW. Compared with some other CMOS multi-modulus prescalers reported lately, our design has demonstrated a considerable improvement in terms of the power-to-speed ratio.