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Geoffrey D. McNiven

dblp:08/4687 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1988
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 75% Performance modeling and evaluation · 25%
Software engineering, system software, and programming languages
1 paper
Compilers and program optimization · 100%

Topics — the 5 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache management
0.011988
Analysis of Memory Referencing Behavior For Design of Local Memories · ISCA 1988
Memory systems
memory referencing behavior
0.011988
Analysis of Memory Referencing Behavior For Design of Local Memories · ISCA 1988
Memory systems › cache management
software-managed cache
0.011988
Analysis of Memory Referencing Behavior For Design of Local Memories · ISCA 1988
Performance modeling and evaluation
trace analysis
0.011988
Analysis of Memory Referencing Behavior For Design of Local Memories · ISCA 1988
Compilers and program optimization › compiler optimization
compiler-directed memory management
0.011988
Analysis of Memory Referencing Behavior For Design of Local Memories · ISCA 1988

Methods — techniques the papers use, named apart from their topics

trace processing · 0.0histogram analysis · 0.0
YearPublicationVenuePosition
1988 Analysis of Memory Referencing Behavior For Design of Local Memories
abstract
Memory-referencing behavior is analyzed by the study of traces for the purpose of developing local memory structures and management techniques. A trace-processing technique called flattening reduces the dependence of the results on the underlying compiler and architecture on which the trace was generated, and partitions each memory location into its constituent values. The referencing patterns of each value in the resulting trace is described using statistics such as interreference time, lifetime, etc. The referencing patterns of the entire trace are described by histograms showing the distributions for the statistics of the individual values. The results of this analysis indicate that the use of a program-controlled cache to efficiently reduce the traffic from the cache to main memory will improve productivity. By using program control, the future knowledge of the compiler can be imparted to the cache, allowing the rejection of dead values and early replacement of values with long interreference times.>
Geoffrey D. McNiven, Edward S. Davidson
ISCA1