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Orin E. Marvel

dblp:08/4784 · DBLP profile ↗
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2ranked-venue papers
2as first author
0since 2021 · last 1974
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 2 first-authorSoftware engineering, systems software and programming languages · 2 · 2 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Parallel and multicore computing · 46% Processor architecture and microarchitecture · 27% Hardware accelerators and domain-specific architectures · 27%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Processor architecture and microarchitecture
special-purpose processor		 0.011974
SPEAC-Special Purpose Electronic Area Correlator · ISCA 1974
Parallel and multicore computing › parallel architecture
associative processor		 0.011973
HAPPE Honeywell Associative Parallel Processing Ensemble · ISCA 1973
Parallel and multicore computing
parallel computing		 0.011973
HAPPE Honeywell Associative Parallel Processing Ensemble · ISCA 1973

Methods — techniques the papers use, named apart from their topics

pipeline ripple-through architecture · 0.0
YearPublicationVenuePosition
1974 SPEAC-Special Purpose Electronic Area Correlator
abstract
In the high data rate systems (> MHz) associated with signal processing, a standard stored program computer is not fast enough. At the present time, parallel (1, 2) and pipeline (3) architectures are being used to solve these computational problems.This paper describes a preprocessor which is optimized to perform sum-of-product operations with a "pipeline ripple through" architecture. A breadboard built to perform the "absolute difference" and "product" correlation functions using this architecture is described.
Orin E. Marvel
 ISCA1
1973 HAPPE Honeywell Associative Parallel Processing Ensemble
Orin E. Marvel
 ISCA1