This work presents a programmable, configurable motion estimation processor for the H.264 video coding standard, capable of handling the processing requirements of high definition (HD) video and suitable for FPGA implementation. The programmable aspect of the processor follows the ASIP (Application Specific Instruction set Processor) approach with a instruction set targeted to accelerating block matching motion estimation algorithms. Configurability relates to the ability to optimize the microarchitecture for the selected algorithm and performance requirements through varying the number and type of execution units at compile time.

This paper describes a novel control system processor architecture based on DeltaSigma modulation known as the DeltaSigma -CSP. The DeltaSigma -CSP utilizes 1-bit processing which is a new concept in digital control applications with the direct benefit of making multi-bit multiplication operations redundant. A simple conditional-negate-and-add (CNA) unit is instead used for operations in control law implementations. For this reason, the proposed processor has a very small silicon footprint and runs at very high frequencies making it ideal for high-sampling rate, real-time control applications. A number of DeltaSigma -CSP configurations have been implemented as VLSI hard macros in a high-performance 0.13-mum CMOS process and a particular configuration achieved a post-route operating frequency of 355 MHz resulting in a 2.17 MHz sampling rate for a fourth-order control law implementation. Additional results prove that the DeltaSigma -CSP compares very favorably, in terms of silicon area and sampling rates, to two other specialized digital control processing systems, including direct, hardwired implementation of control laws; at the same time, it substantially outperforms software implementations of control laws running on very wide, general-purpose VLIW architectures.

This paper presents a DVS (Dynamic Voltage Scaling) enabled SoC (System-on-Chip) processing platform based on the Leon3 open-source processor and dynamically reconfigurable clock synthesis technology available in Virtex-4 Xilinx FPGAs. A special DVS monitor unit maintains correct operation of the processor core at a given voltage by tracking the behavior of an internal delay line and stopping the processor clock through a digital clock management (DCM) macroblock when a timing error is about to occur. Upon detection of a new valid working point the DVS monitor unit reconfigures the main DCM to synthesize a new frequency-adjusted CPU clock signal and reactivates the processor. The energy savings and operation range of the technology are evaluated in the context of video coding applications by executing different motion estimation kernels.

This paper presents a detailed analysis of the behavior of a novel fault-tolerant 32-bit embedded CPU as compared to a default (non-fault-tolerant) implementation of the same processor during a fault injection campaign of single and double faults. The fault-tolerant processor tested is characterized by per-cycle voting of microarchitectural and the flop-based architectural states, redundancy at the pipeline level, and a distributed voting scheme. Its fault-tolerant behavior is characterized for three different workloads from the automotive application domain. The study proposes statistical methods for both the single and dual fault injection campaigns and demonstrates the fault-tolerant capability of both processors in terms of fault latencies, the probability of fault manifestation, and the behavior of latent faults.

This paper introduces a novel genetic algorithm whose properties have been purposely designed to be suited to hardware implementation. This is distinct from previous hardware designs that have been realized directly from conventional genetic algorithm approaches. To be suitable for hardware implementation, we propose that a genetic algorithm should attempt to both minimize final layout dimensions and reduce execution time while not compromising algorithmic performance. Consequently, the new genetic algorithm specifically aims to keep the requisite silicon area to a minimum by incorporating a monogenetic strategy that retains only the optimum individual, resulting in a dramatic reduction in the memory requirement and obviating the need for crossover circuitry. The results given in this paper demonstrate that new approach improves on a number of existing hardware genetic algorithm implementations in terms of the quality of the solution produced, the calculation time and the hardware component requirements.

A high performance and silicon efficient hardware architecture for binary arithmetic coding (BAC) acceleration is presented and its application to entropy coding in the context of the H.264 video compressor standard described. The proposed hardware architecture remains bit compatible with the software implementation used in the H.264 ITU standard. The renormalization sequence that maintains the state variables in the appropriate range has been rewritten in order to enable a data independent throughput in hardware of 1 symbol per clock cycle. The instruction set extensions required to be implemented as part of the ISA of a controlling RISC are proposed. Finally, ASIC and FPGA implementations are obtained and the performance and complexity compared with recent implementations of the well-known MQ-coder reported.

This paper presents a practical realization in hardware of the concepts of variable order Markov modeling using multisymbol alphabets and arithmetic coding for lossless compression of universal data. This type of statistical coding algorithm has long been regarded as being able to deliver very high compression ratios close to the information content of the source data. However, their high computational complexity has limited their practical application in embedded environments such as in mobile computing and wireless communications. In this paper, a hardware amenable algorithm named PPMH and based on these principles has been developed and its architecture and implementation detailed. This novel lossless compression core offers innovative solutions to the computational issues in both stages of modeling and coding and delivers high compression efficiency and throughput. The configurability features of the core allow efficient use of the embedded SRAM present in modern FPGA technologies where memory resources range from a few kilobits to several megabits per device family. The core has been targeted to the Altera Stratix FPGA family and performance, coding efficiency, and complexity measured for different memory configurations.