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Carsten Oetker

dblp:08/5170 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 2000
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 87% Reconfigurable computing and FPGAs · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › power estimation
FPGA power estimation
0.012000
Power estimation approach for SRAM-based FPGAs · FPGA 2000
Electronic design automation
power estimation
0.012000
Power estimation approach for SRAM-based FPGAs · FPGA 2000
Reconfigurable computing and FPGAs
FPGA architecture
0.012000
Power estimation approach for SRAM-based FPGAs · FPGA 2000

Methods — techniques the papers use, named apart from their topics

emulation · 0.0benchmark design · 0.0
YearPublicationVenuePosition
2000 Power estimation approach for SRAM-based FPGAs
abstract
This paper presents the power consumption estimation for the novel Virtex architecture. Due to the fact that the XC4000 and the Virtex core architecture are very similar, we used the basic approaches for the XC4000-FPGAs power consumption estimation and extended that method for the new Virtex family. We determined an appropriate technology-dependent power factor Kp to calculate the power consumption on Virtex-chips, and developed a special benchmark test design to conduct our investigations. Additionally, the derived formulas are evaluated on two typical industrial designs. Our own emulation environments called SPYDER-ASIC-X1 and SPYDER-VIRTEX-X2 were used, which are best suited for the emulation of hardware designs for embedded systems.
Karlheinz Weiß, Carsten Oetker, Igor Katchan, Thorsten Steckstor, Wolfgang Rosenstiel
FPGA2