Convolutional neural networks (CNNs) face the challenges of model parameter expansion and surging computing resource requirements in complex visual tasks. The traditional von Neumann architecture leads to frequent data interaction due to the separation of storage and computing, while in-memory computing (PIM) significantly reduces latency and energy consumption through in-situ computing. However, it still faces two key problems in the actual reasoning process: inefficient weight block mapping increases the computing cycle, and repeated transmission of feature maps under the convolution sliding window mechanism. Both of them exacerbate the reasoning delay.

Hardware description languages (HDLs) are pivotal for the development of hardware designs. The programming courses for HDLs are also popular in both universities and online course platforms. Similar to programming assignments of software languages (SLs), these of HDLs also actively call for automated program repair (APR) techniques to provide personalized feedback for students. However, the research of APR techniques targeting HDL programming assignments is still in an early stage. Due to the significantly different programming mechanism of HDLs from SLs, the only APR technique (i.e., CirFix) targeting HDL programming assignments contributes a customized repair pipeline. However, the fundamental challenges in the design of HDL-oriented fault localization and patch generation still remain unresolved. In this work, we propose a signal value transition-guided defect repair technique named STRIDER by capturing the intrinsic features of HDLs. This technique consists of a time-aware dynamic defect localization approach to precisely localize defects, and a signal value transition-guided patch synthesis approach to effectively generate fixes.We further construct a dataset of 57 real defects from HDL programming assignments for tool evaluation. The evaluation reveals the overfitting issue of the pioneering tool CirFix and the significant improvement of STRIDER over CirFix in terms of both effectiveness and efficiency. In particular, STRIDER is more effective by correctly fixing 2.3X as many defects as CirFix in the real defect dataset, and is 23X more efficient by generating a correct fix within five minutes on average in the synthetic defect dataset, while CirFix takes around two hours on average.

Coverage guided dynamic verification is a widely used verification technique for RTL designs described using domain-specific languages for hardware and representing in some intermediate representations. Although the embedding of fuzz testing promote the abilities of coverage guided dynamic verification, there are lack of efficiently metric feedbacks utilization. In this paper, we proposed MMFuzz, a novel fuzzing tool enhanced by metric feedbacks. The proposed method utilze metric feedbacks efficiently in two aspects: seeds selection and mutators selection. The experimental results on several practical designs show that our method is able to achieve up to 1.0x improvements over the state-of-the-art RTL fuzzing tool with the same times of mutation.

With the successful application of hardware agile design methodology, it has become a big challenge to optimize the design in novelly defined intermediate representations (IR), such as FIRRTL. However, there is little work focusing on this challenge, or the optimization tasks are left to logic synthesizers by translating IRs into designs in hardware description languages (HDL).

Dynamic verification method is still the most easily accessible and thus heavily used verification approach for System-on-Chip (SoC) designs. Assertions are widely used in dynamic verification for functional coverage analysis. At present, how to generate tests to effectively cover assertions defined over internal signals is still a challenge for dynamic verification. In this paper, we propose a novel test generation method to accelerate assertion coverage using surrogate logic model. A surrogate logic model is used to represent an approximate relationship between an internal signal and related input signals, which is derived from simulation results by using machine learning technology. With surrogate logic model, we transfer the test generation for assertion coverage problem to a random sampling problem and solve it by the state-of-the-art sampling techniques. Experimental results on diverse benchmarks demonstrate that the proposed method could accelerate assertions coverage in two aspects, one is covering an assertion as quick as possible and the other is covering an assertion more times in a given period.

Recently, hardware agile design methods have been developed to improve the design productivity. However, the mod-eling methods hinder further design productivity improvements. In this paper, we propose and implement a microprocessor agile design method using feature oriented programming technology to improve design productivity. In this method, designs could be uniquely partitioned and constructed incrementally to explore various functional design features flexibly and efficiently. The key techniques to improve design productivity are flexible modeling extension and on-the-fly feature composing mechanisms. The evaluations on RISC- V and OR1200 CPU pipelines show the effectiveness of the proposed method on duplicate codes reduction and flexible feature composing while avoiding design resource overheads.

In this work-in-progress innovative practice paper, we argue the application-ability training in Discrete Mathematics (DM) should be enhanced for students majoring in computing science. Our motivation is based on the analysis of the differences in learning outcomes between DM and other branches of Math courses, the special role of DM in computer science (CS) courses and the gaps between DM and other CS courses. Motivated by the above analysis, we rethink of CS undergraduate education program as a DM-centric program. Furthermore, we make an experimental implementation of the DM-centric program and enhance application-ability training by designing and adopting many large-scale projects from various related topics, such as database, satisfiability, deductive proof and so on. Each project is decomposed into several sub-projects, which are integrated with a project-based learning environment. The large-scale projects derived from related CS courses enable students to get in touch with various computing topics related to DM applications at an early stage in the learning process. The learning environment with the ability of automatic assessment enables students to complete the projects in a step-by-step manner. The preliminary feedback from 219 students after taking the redesigned DM course shows the promising effects on students' following learning.

With the ending of Moore's Law and Dennard scaling, modern System-on-a-Chip (SoC) trends to incorporate a large and growing number of specialized modules for specific applications. Verification is vital to the RTL design and faces new challenges due to the growing design complexities. In this paper, we proposed a symbolic simulation enhanced coverage- directed dynamic verification technique for RTL designs. We proposed novel Full Multiplexer Toggle Coverage (FMTC) to trace and provide feedback to the verification process. The proposed method is a hybrid between symbolic simulation and mutation based fuzz testing that offsets the disadvantages of both. The achievement of high coverage is obtained by interleaved symbolic simulation and fuzz testing passes. The symbolic simulation pass is used to generate tests that direct the testing to untouched corners. While the mutation based fuzz testing pass is used to leverage test generation tasks and to enable the method to deal with large scale designs. The empirical evaluation of the method shows promising results on archiving high coverage for practical designs.

Soft errors have become a critical challenge as a result of technology scaling. However, to evaluate the influence of soft errors in flip-flop (FF) on the failure of circuit is a hard verification problem. Here, we proposed a novel flip-flop soft error failure rate analysis methodology using sequential equivalence checking (SEC) and taking the application behaviors into consideration, which combines the advantage of formal techniques based approaches in completeness and the advantage of application behaviors in accuracy in differentiating vulnerability of FFs. As a result, all the FFs in a circuit are sorted by their failure rates and designers can use this information to perform optimal hardening of selected sequential components against soft errors. Experimental results on an implementation of a SpaceWire end node and the set of the largest ISCAS'89 benchmark sequential circuits demonstrate the efficiency of our approach. Case study on an instruction decoder of a practical 32 bits microprocessor shows the applicable of our methodology.

The growing design-productivity gap has made designers shift toward using high-level synthesis (HLS) techniques to generate register transfer level design from high-level languages. Unfortunately, this translation process is very complex and may introduce bugs into the generated design, which can create a mismatch between what a designer intends and what is actually implemented in the circuit. In this paper, we present an equivalence checking method to validate the result of HLS scheduling against the initial high-level program. Finite state machine with data path (FSMD) models were used to represent designs before and after scheduling. The proposed method uses a bisimulation relation approach to prove equivalence. The automatically established bisimulation relation guarantees that for each execution sequence in the design before scheduling, a related and equivalent execution sequence exists in the design after scheduling and vice versa. Our method provides a unified way to deal with various scheduling optimizations. We have implemented our validation technique and compared it with a state-of-the-art HLS scheduling verification method. The promising results show the effectiveness and efficiency of our method.

In this poster, we report our experience in teaching introductory courses on programming based on program derivation using formal method. Based on an ongoing teaching activity, we present some preliminary results on the students' experiences.

Functional verification is widely recognized as the bottleneck of the hardware design cycle. The coverage-driven verification approach makes coverage the core engine that drives the whole verification flow, which enables reaching high quality verification in a timely manner. In this paper, we present a coverage driven test generation methodology and a set of tools. We present a novel method for automatic generating simulation vectors from HDL descriptions based on path coverage and constraint solving. We present a novel approach to generate functional vectors based on assertions for RTL design verification. Our approach combines program-slicing based design extraction, word-level SAT and dynamic searching techniques. We also present a coverage analysis method based on VCD file, which only replaying the simulation of the control statements in the HDL description. Experimental results show the efficiency of our methodology.

We designs and implements a system-on-chip SW/HW co-verification environment SoC-Gen, which collaborates formal verification and simulation techniques for SoC co-verification. This paper first give an overview of SoC-Gen, and then focus on the simulation based verification environment: SoC-CBSHVE, which based on componential design and integration methodology The environment adopts automatic software, hardware and simulation wrappers. Simulator adopts asynchronous parallel algorithm and bus-based communication mechanism. Five data buses support verification components simulation communication. Standard message format and unify simulation interfaces easy SoC components design and verification. Experimental results show that SoC-CBSHVE enables easy debugging, rich portability, and high verification speed, at a low cost for system-on-chip system-level software and hardware co-verification.

A novel specification driven and constraints solving based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper. Our microprocessor architectural automatic test program generator (MA2TG) can produce not only random test programs but also a sequence of instructions for a specific constraint by specifying a user constraints file. The proposed methodology makes three important contributions. First, it simplifies the microprocessor architecture modeling and eases adoption of architecture modification via architecture description language (ADL) specification. Second, it generates test programs for specific constraints utilizing the power of state-to-art constraints solving techniques. Finally, the number of test program for microprocessor verification and the verification time are dramatically reduced. We applied this method on DLX processor to illustrate the usefulness of our approach.

This paper presents a novel method for automatic functional vectors generation from RT-level HDL descriptions based on path coverage and constraint solving. Compared with existing method, the advantage of this method includes: 1) it avoids generating redundant constraints, which will accelerate the test generation process, 2) it solves the problem of how to propagate the internal values to the primary inputs with decision models, 3) it can handle various HDL description styles, and various styles of designs. Experimental results conduct on several practical designs show that our method can efficiently improve the functional vectors generation process. The prototype system has been applied to verify RTL description of a real 32-bits microprocessor core and complex bugs remained hidden in the RTL descriptions are detected.

A novel specification driven and constraints solving based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper. Our microprocessor architectural automatic test program generator (MA/sup 2/TG) can produce not only random test programs but also a sequence of instructions for a specific constraint by specifying a user constraints file. The proposed methodology makes three important contributions. First, it simplifies the microprocessor architecture modeling and eases adoption of architecture modification via architecture description language (ADL) specification. Second, it generates test programs for specific constraints utilizing the power of state-to-art constraints solving techniques. Finally, the number of test program for microprocessor verification and the verification time are dramatically reduced. We applied this method on DLX processor to illustrate the usefulness of our approach.

We present a novel approach to generate functional vectors based on assertions for RTL design verification. Our approach combines program-slicing based design extraction, word-level SAT and dynamic searching techniques. Through design extraction, vectors generation need only concern about the design parts related to the given assertion, thus large practical designs can be handled. Constraints Logic Programming (CLP) naturally models mixed bit-level and word-level constraints, and word-level SAT techniques solve the mixed constraints in a unified framework, which gain perfect performance. Initial states derived from dynamic simulation can dramatically accelerate the searching process of functional vectors generation. A prototype system has been built, and the experimental results on some public benchmarks and industrial circuits demonstrate the efficiency of our approach and its applicability to large practical designs.

For RTL verification, we have to separate the control and datapath parts contained in the whole design, and apply different verification techniques for different parts. This paper presents a new circuit extraction method using program slicing technique, and develops an elegant theoretical basis based on program slicing for circuit extraction from Verilog description. The technique can obtain a chaining slice for given signals of interest. Compared with related researches, the main advantages of our method include: it is fine grain; it has no HDL coding style limitation; it is precise and is capable of dealing with various Verilog constructions. The technique has been integrated with a commercial simulation environment and incorporated into a design process. The experimental results on practical designs show the significant benefits of the proposed approach.