The Register level Test Generator (RTG) system is a software tool that automatically develops test patterns to detect all classical single “stuck-at” faults in a digital circuit. In its current state RTG is targeted for boards containing SSI, MSI, and small LSI components. RTG combines an efficient technique for modeling sequential components at the register level with a simple set of testability design rules, and a powerful test generation algorithm. Thus far in its development RTG has been shown to be a useful tool, typically capable of generating a 100% fault coverage test for a 50 IC board in about 30 CPU minutes on a VAX1 11/780 running UNIX.2

This paper focuses on automatic synthesis of digital hardware from a behavioral description. Algorithms have been written and tested to perform automatic generation of control hardware and optimized microcode for specified data paths. The optimization algorithms produce a family of results based on cost and speed constraints supplied by the user. The algorithms adapt to these constraints and adjust the amount of parallelism in the synthesized microcode accordingly. Tests were run by generating microcode for a PDP-11/40. Results compared favorably with the human design.

This paper is a tutorial intended primarily for individuals just getting started in digital testing. Basic concepts of testing are described, and the steps in the test development process are discussed. A pragmatic approach to test sequence generation is presented, oriented towards ICs interconnected on a board. Finally, design for testability techniques are described, with an emphasis on solving problems that appeared during the test generation discussion.

This paper presents a facility for the description and simulation of the inner machine of microprogrammable processors. The use of this facility for teaching microprogramming and for research is discussed. Twelve simulations are described, and an example simulation shown. Observations about the research are presented, and future research outlined.