Kailiang Xu

dblp:08/7089 · also Kai-Liang Xu · DBLP profile ↗
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5ranked-venue papers
2as first author
3since 2021 · last 2026
—ORCID · conflict

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 2 first-authorSystems, architecture and hardware · 2 · 2 since 2021Software engineering, systems software and programming languages · 1 · 1 since 2021

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 54% Cloud and datacenter computing · 46%
Computer networks
1 paper
Internet architecture and protocols · 50% Routing and switching · 50%

Topics — the 8 heaviest of 9, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache
1.012026
SpiderSense: Lightweight Last-Level Cache Management via Time Period Tagging for LLC-Critical Workloads · ACM Trans. Archit. Code Optim. 2026
Memory systems › cache management
cache partitioning
1.012026
SpiderSense: Lightweight Last-Level Cache Management via Time Period Tagging for LLC-Critical Workloads · ACM Trans. Archit. Code Optim. 2026
Memory systems › memory hierarchy › cache hierarchy
last-level cache
1.012026
SpiderSense: Lightweight Last-Level Cache Management via Time Period Tagging for LLC-Critical Workloads · ACM Trans. Archit. Code Optim. 2026
Cloud and datacenter computing › multi-tenancy
multi-tenant cloud
1.012026
SpiderSense: Lightweight Last-Level Cache Management via Time Period Tagging for LLC-Critical Workloads · ACM Trans. Archit. Code Optim. 2026
Cloud and datacenter computing
performance isolation
1.012026
SpiderSense: Lightweight Last-Level Cache Management via Time Period Tagging for LLC-Critical Workloads · ACM Trans. Archit. Code Optim. 2026
Routing and switching › qos routing
priority routing
0.912025
To PRI or Not To PRI, That's the question · OSDI 2025
Cloud and datacenter computing
virtualization
0.312026
SpiderSense: Lightweight Last-Level Cache Management via Time Period Tagging for LLC-Critical Workloads · ACM Trans. Archit. Code Optim. 2026
Cloud and datacenter computing › virtualization
virtual machine monitor
0.312026
SpiderSense: Lightweight Last-Level Cache Management via Time Period Tagging for LLC-Critical Workloads · ACM Trans. Archit. Code Optim. 2026

Methods — techniques the papers use, named apart from their topics

time period tagging · 1.0dynamic sampling · 1.0
YearPublicationVenuePosition
2026 SpiderSense: Lightweight Last-Level Cache Management via Time Period Tagging for LLC-Critical Workloads
abstract
Multi-tenant clouds enhance resource sharing among Virtual Machines (VMs) to boost overall utilization and reduce power consumption. However, this also introduces interference among workloads from different tenants and impedes VM performance isolation. In this article, we first demonstrate that the last-level cache (LLC) in CPUs, which is inherently shared by all VMs on the same physical machine, becomes a significant contending resource for LLC-critical workloads, leading to notable performance imbalances under the default hardware caching strategy. Although recent studies on LLC scheduling have progressed, they often require detailed profiling of user workloads or rely on hyperparameter tuning, limiting their applicability to private clusters or specific scenarios. We propose SpiderSense, a software-initiated LLC partitioner for managing Virtual Machine Monitors (VMM), to address these limitations. SpiderSense leverages modern yet off-the-shelf server CPU features to adaptively orchestrate LLC allocation among running black-boxed user VMs. SpiderSense dynamically samples VMs and calculates their fair share of LLC to allocate them while fully improving performance isolation among VMs. We experiment with SpiderSense using typical LLC-critical workloads, representative of the types of applications that stress LLC performance, such as Memcached and Llama. Our results show that SpiderSense improves performance by up to 40% in numerous colocation scenarios compared to current solutions.
Zhixiang Wei, Zhibai Huang, James Yen, Tianlei Xiong, Kailiang Xu, Yucheng Zheng, Xingzi Yu, Yun Wang 0039, Zhengwei Qi
ACM Trans. Archit. Code Optim.5
2025 DevTrace: Lightweight Plug-In Design for PCIe Transaction Tracing in Edge Intelligence Workloads
abstract
The complexity of host-peripheral interactions during high-load tasks poses significant challenges for system optimization, with existing tracing tools degrading performance by up to 5.39×. We introduce DevTrace, a novel low-overhead tracing framework for peripheral interactions. Its modular architecture separates data collection from kernel-level operations, enabling lightweight tracing with minimal driver modifications across entire classes of devices. By eliminating heavy kernel tracing interrupts, DevTrace reduces overhead to negligible levels while maintaining data accuracy. In edge-based intelligence deployments, DevTrace achieves a 128× reduction in memory usage and approximately 10× lower CPU overhead compared to page-fault-based solutions. It significantly reduces data loss and performance degradation under high-load conditions, establishing it as a reliable tool for analyzing host-peripheral interactions and optimizing performance in resource-constrained environments. We also discuss potential extensions to eBPF to further decouple tracing from driver frameworks.
Zhibai Huang, Kailiang Xu, Zhixiang Wei, Yinghao Deng, Chen Chen 0067, Yun Wang 0039, Fangxin Liu, Mingyuan Xia 0001, Zhengwei Qi
ICCAD2
2025 To PRI or Not To PRI, That's the question
Yun Wang 0039, Xianting Tian, Ben Luo, Zhixiang Wei, Zhibai Huang, Kailiang Xu, Kaihuan Peng, Kaijie Guo, Guangjian Wang, Shengdong Dai, Yibin Shen, Jiesheng Wu, Zhengwei Qi
OSDI8
2017 Parallel-machine Scheduling with Precedence Constraints and Controllable Job-processing Times
Kailiang Xu, Rong Fei
ICORES1
2015 Schedule Two-machine Flow-shop with Controllable Processing Times Using Tabu-search
Kailiang Xu
ICORES1