Demonstration venue · read-only. Every page can be browsed; the buttons that would change it are switched off. Create an account to run TaxoReview on your own data. A simulation from public publication records: the people listed were not invited and did not agree to review.
? Tutorial for this page
Demo Data from VLDB 2026 / reviewers in the wild / expert

Juraj Povazanec

dblp:08/845 · DBLP profile ↗
← Back
3ranked-venue papers
1as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 100%

Topics — the 2 heaviest of 2, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Integrated circuit design
asynchronous circuit design		 0.012001
A New Control Circuit for Asynchronous Micropipelines · IEEE Trans. Computers 2001
Integrated circuit design › asynchronous circuit design
micropipeline		 0.012001
A New Control Circuit for Asynchronous Micropipelines · IEEE Trans. Computers 2001
YearPublicationVenuePosition
2002 Integration of SRAM Redundancy into Production Test
abstract
In this paper, we present the implementation of a multiple-SRAM redundancy concept, which increases the yield of a 100 mm/sup 2/, 0.18 micron technology device with a total memory size of 3 Mbits, by a factor of 20%. A number of test and design considerations are detailed.
Jayasanker Jayabalan, Juraj Povazanec
 ITC2
2001 A New Control Circuit for Asynchronous Micropipelines
abstract
In this paper, we present a new configuration of an asynchronous micropipeline, called locally distributed asynchronous (LDA) micropipeline, using a new control circuit. The control circuit generates local control signals according to the 4-phase signaling protocol. The control circuit is used to control the dynamic logic in the datapath. Comparisons based on simulations with other earlier published asynchronous micropipelines are also presented.
Oliver Chiu-sing Choy, Jan Butas, Juraj Povazanec, Cheong-Fat Chan
 IEEE Trans. Computers3
1997 Fault and test-process modelling for integrated circuits
Juraj Povazanec, Vladislav Musil
 J. Syst. Archit.1