An increase in temperature and pressure can cause spontaneous ignition of the air-fuel mixture in internal combustion engines, reducing engine efficiency, lifespan, and increasing air pollution. Typically, to predict and detect this effect, a knock sensor is used, which has a low detection accuracy due to the engine vibration noise. In this work, a machine learning model based on a meta-classifier is proposed and implemented for real-time fault detection in combustion engines. First, actual knock sensor data are recorded at diverse engine speeds from our engine test bench. The local dataset is preprocessed and scaled. Then, 30 different features in the time and frequency domains are investigated. Dimensionality of data is reduced employing recursive feature elimination. Then, a stacking classifier is utilized to address the classification problem by combining several classification models through the use of a metaclassifier. To enhance the assessment of the experimental outcomes in knock detection, k-fold cross-validation is utilized to gauge the model's performance with new data. The result shows the proposed method has around 12% higher accuracy during 5 cross folds with least amount of variation. Finally, the model is implemented on an ARM MCU and showed an execution time of 8.9ms, which validates its reliability for real-time operation.

A switched constant current driver for a configurable switch network based on electrothermal micro-electromechanical-systems (MEMS) components is presented. A constant current-mode approach is proposed for achieving precise power control over an array of devices that leverage thermal heaters for actuation. This multi-channel actuation circuit is able to power different electrothermal MEMS switches. Interface circuits based on the self-temperature sensing technique of the heater and the ohmic contact property of the actuator are proposed. They provide early detection to address MEMS lifetime concerns, and constitute the main novelty of this research, which is specifically focused on the application. The circuit is implemented in a 0.18 μm BCD technology and occupies an area of 1.3 mm2. Post-layout simulations show that the system can output current up to 90 mA (Rheater= 80 Ω) with a resolution of 2 mA.

A selective harmonic elimination pulse width modulation (SHEPWM) class-D amplifier (CDA) with a reconfigurable gate driver integrated circuit (IC) is proposed. The H-bridge CDA generates a three-level SHEPWM signal and cancels lower order harmonics of the switching voltage. To generate accurate pulses at the right switching angles, GaN devices are used and a reconfigurable gate driver IC is used to control the driving strength of the gate driver. The SHEPWM algorithm is implemented in an FPGA and can configure the output on-the-fly. The simulation results show that the SHEPWM CDA has a 0.48 % total harmonic distortion (THD) for a 10 kHz output with an estimated switching loss of 38 mW for a GaN power transistor. It also shows that the driving strength of the gate driver has very little effect on THD, therefore the driving strength can be optimized between overshoot voltage and switching loss without concern for THD.

The Secure Hash Algorithm-256 (SHA-256) is a cryptographic function used in a wide variety of applications ranging from Internet of Things micro-devices to highperformance systems. This paper studies a set of implementations of the SHA-256 on a field-programmable gate array (FPGA) elaborated using the Open Computing Language (OpenCL). These implementations apply several optimization techniques to improve their respective throughputs. Reported results show that a combination of OpenCL optimization techniques allows obtaining an implementation offering a 90x speed-up when compared to an unoptimized OpenCL implementation. Moreover, the best reported optimized implementation achieves a throughput of 3973 Mbps, which is 4.3 times higher than the best previously published HLS-based SHA-256 implementation and even higher than the previously published implementations using a hardware description language. To our knowledge, this work is the first that proposes an OpenCL-based FPGA implementation of SHA-256 and its OpenCL-based optimization methodology.

This paper presents a new dual-inductor hybrid boost converter (DI-HBOC) with two inductors located at the output. This structure allows continuous current delivered to the load, thus, reducing the output filtering capacitor size and the output voltage ripple. By relocating the inductor at the output, which is the lower current path, the conduction loss on the inductor can be significantly reduced. The right half plane zero (RHPZ) in the control-to-output transfer function can also be eliminated; therefore, a simple pulse-width modulation (PWM) voltage-mode controller can be used for the proposed DI-HBOC while still achieving high closed-loop bandwidth and fast transient response. The distinct features of the proposed converter are analytically demonstrated. A 12-to 24 V DI-HBOC and a conventional BOC (CBOC) using low-ÆoN GaN switches with PWM voltage-mode controller are also implemented in PSIM for verification and comparison. The simulated peak power efficiency is 97.4 % that is 1.17 % higher than the CBOC. At 3 A load current, the power efficiency is improved by 9.7 % and the output ripple is only 17.5 mV, 6x lower than in CBOC.

This paper presents a novel and compact bandgap comparator (BGRCOMP) for under-voltage lockout (UVLO) and thermal shutdown (TSD) protection circuits. The proposed BGRCOMP is self-referenced and combines the advantages of both a high-accuracy bandgap reference and a comparator into one single circuit. A latch-controlled biasing technique is also presented, which reduces static power consumption of the proposed BGRCOMP. The proposed BGRCOMP is used for the design of compact and low power UVLO and TSD circuits. The post-layout simulation results using a 0.18 μm BCD-on-SOI technology prove the attractive performance of the UVLO and TSD with a static current (Iq) of 7.76 μA and 5.4 μA from a 5 V supply, respectively. The deviations of UVLO thresholds are less than 3 mV in the temperature range of -40~85 °C.

This paper presents a compact configurable power control system for safety-critical applications, which operates in harsh environments. This heterogeneous integrated mixed digital, analog and high-voltage design for power applications is implemented in a system-in-package (SiP) module using a low-temperature co-fired ceramics (LTCC) substrate. A comparison between technologies for SiP designs shows that LTCC is advantageous in terms of integration density, thermal and electrical performances, as well as signal and power integrity. In addition, this work proposes layout and fabrication techniques for the enhancement of thermal, electrical performances and integration density specific to LTCC-based designs, such as chip-covering, multi-layer routing of power signals and self-damped transmission lines. An improvement of 59% in available area, 32% reduction of temperature due to self-heating, 65% loss reduction and 22% reduction in interference coupling were obtained when compared to a baseline design.

This paper presents a new in-system circuit for monitoring and profiling OpenCL-based designs on FPGA. This circuit opens the door for improved monitoring of OpenCL-based FPGA accelerators. The monitoring approach allows designers to identify unexpected performance bottlenecks such as pipeline stalls and initiation interval in OpenCL loops. The proposed monitor enhances observability into OpenCL-based accelerators by capturing high-level hardware events and timing information at FPGA-clock accuracy. Any event or variable in an OpenCL kernel can be observed by instantiating monitor circuits specified in OpenCL. To our knowledge, it is the first FPGA clock-cycle accurate monitor that can select not only the variables, but also the data inputs to be monitored in such variables. To validate the proposed in-system monitoring circuit, the Arria10 FPGA and Intel SDK were used for the OpenCL tool-chain. The reported results show that the presented monitoring circuit introduces a frequency degradation that remains small for 8 tested monitors instances. These monitors use 2.3 times fewer logic resources than previously reported OpenCL monitors.

A novel defect-tolerant network of digital-to-analog converters (DACs) is presented in this paper. The architecture of this converter employs a single 2.5-V voltage reference and an unbalanced buffering technique to achieve a wide voltage range that extends from 864 mV to 2.538 V with an 8-bit resolution. The proposed converter incorporates a defect-tolerant architecture and is extremely compact, utilizing a per-bit silicon area of less than 350 μm2. Although such very small area allows for embedding in dense configurable fabrics (field-programmable gate arrays) and wafer-scale integration, the overall performance is not sacrificed as reported measurements show a signal-tonoise ratio of 51.87 dB and a spurious-free dynamic range of 42.31 dB, at 10 MS/s providing 7.6 effective bits. Moreover, the proposed architecture benefits from dynamic calibration capabilities, as any converter output can be finely adjusted over a range of 25 mV. This proposed DAC is also extensively reused in the same defect-tolerant network for a successive approximation register-analog-to-digital converter, as well as for a configurable voltage reference.

In this paper, an area efficient time to digital converter (TDC) performing measurements between multiple hit signals is proposed. Our TDC is based on a delay line configured as a ring oscillator and a round tracker to count the number of iterations through the oscillator. Lookup tables configured as distributed RAMs and shift registers are used to sample the oscillator and the round tracker states whenever a transition on a signal occurs. A theoretical study is elaborated to estimate FPGA resources required to implement the proposed TDC in comparison with a multichannel basic RO-TDC. It is shown that the gain in the number of Flip-Flops and Lookup tables can reach factors of 85 and 2.1 respectively in an architecture made of a six-stage oscillator, a 32-state round tracker and 20 input hit signals. Temporal characteristics extracted from our TDC implemented in a Xilinx ZYNQ family FPGA are reported.

This paper presents a spatially configurable input stage for differential-to-single ended conversion enabling signal propagation through single ended field programmable interconnection networks. The input stage uses current mode sensing for differential-to-single ended conversion. Compared to voltage mode sensing, it can support higher common-mode input voltage. Post-layout Monte-Carlo simulations show that the input stage can support data rates of up to 2 Gbps and 1 Gbps for an input common-mode voltage of 1.2-1.6 V and 1.2-2.0 V respectively. The input stage was laid out in a mature 0.13 μm CMOS technology and reported results demonstrate that the occupied silicon area is 22 times smaller than that required by a differential input stage based on unity-gain buffer multiplexers.

Algorithms are proposed to diagnose defects in a defect tolerant field programmable interconnection network embedded in a large area integrated circuit. The proposed diagnosis algorithms use a diagonal configuration approach to reduce the cone of influence of individual tests, thus allowing parallel tests according to diagonal patterns. The proposed algorithms avoid redundant diagnosis tests. Efficiency of the proposed diagnosis algorithms are calculated in terms of the number of cycles of a JTAG FSM required to apply the test. Results show a 113-fold test time reduction in the considered interconnection network.

This paper presents a new and highly efficient approach for the estimation by fault injection of the sensitivity to Single Event Upsets of circuits implemented in Xilinx SRAM-based FPGAs. The proposed approach prioritizes fault injection in specific configuration bits subsets defined according to their contents and the type of FPGA resources that they are configuring. The new approach also allows maximizing either the number of critical bits flipped during the injection or the estimation accuracy of the critical bits number. The results show that the new approach outperforms the traditional random fault injection with speed up factors up to two orders of magnitude.

In this paper, a novel technique to get a defect tolerant JTAG compliant scan chain in very large area integrated circuits (VLAIC) is presented. It was ruled that wafer-scale VLAICs require structural regularity and defect-tolerance to be cost effective. Using only one scan chain, as typically used in PCBs, would make the whole VLAIC unusable if a single defect is present in the chain. The proposed technique regularly distributes JTAG Test Access Port (TAP) controllers with test data ports linked to two or more neighbor test data ports. One TAP controller is wired as the entry point and another as the exit point of the scan chain that must be configured according to defect locations. An externally controlled wormhole like routing algorithm can be used for functional link discovery. This paper also proposes a mechanism to make defect tolerant access to test data registers, controlled from neighbor TAP controllers. Our technique has been successfully implemented and validated in a wafer-scale like integrated circuit used in a platform for electronic system prototyping. The logic area of this defect-tolerant configurable JTAG scan chain technique occupies 5% of the test logic and 0.3 % of the cell logic when links to four nearest neighbors are included.

This paper presents a circuit proposed for the DreamWaferTMtechnology. This circuit can interconnect several pads, also called NanoPads, in such a way that they can imitate the behavior of a single metal line for open-drain (or open-collector) buses compliant to the I2C protocol. Thus, multiple serial data lines (SDA) and serial clock lines (SCL) from different user ICs can be connected together on the WaferboardTM. The interface can support up to 25 I2C IC pins together. It can support bidirectional data transfers at up to 100 kbit/s in the Standard-mode, up to 400 kbit/s in the Fast-mode, up to 1 Mbit/s in the Fast-mode Plus, or up to 3.4 Mbit/s in the High-speed mode. The entire interface would take less than 1% of the total area of the WaferICTM, the target system environment for which this circuit is proposed.

We describe, in this paper, a new digital input-output power configurable PAD (CPAD) for a wafer-scale-based rapid prototyping platform for electronic systems. This wafer-scale platform includes a reconfigurable wafer-scale circuit that can interconnect any digital components manually deposited on its active alignment-insensitive surface. The whole platform is powered using a massive grid of embedded voltage regulators. Power is fed from the bottom side of the wafer using through silicon vias. The CPAD can be configured to provide CMOS standard voltages of 1.0, 1.5, 1.8, 2.0, 2.5, and 3.3 V using a single 3.3 V power supply. The digital I/O includes transistors sharing and is embedded within the regulation circuit by combining it with a turbo mode that insures high-speed operation. Fast load regulation is achieved with a 5.5-ns response time to a current step load for a maximum current of 110 mA per CPAD. The proposed circuit architecture benefits from a hierarchical arborescence topology where one master stage drives 16 CPADs with a very small quiescent current of 366 nA. The CPAD circuit and the master stage occupy a small area of 0.00847 and 0.00726 mm2, respectively, in CMOS 0.18-μm technology.

The concept of sending and receiving analog signals through a digital interconnection network is presented in this paper. The proposed “analog bus” addresses limitations of a novel rapid prototyping platform called the WaferBoard™ that was initially designed to support prototyping of all digital circuits with its embedded fully digital interconnection network. This paper explores the simplest and least area consuming means of propagating analog signals through a digital interconnection network. A prototype integrated circuit based on the proposed concept was designed using the TSMC 0.18µm technology. The presented prototype is capable of sending an analog signal in the range of 0.6 V to 1.6 V with a maximum frequency of 200 kHz while consuming 68×53.4 µm2of chip area and 19.9 mW of power.

A new approach for pin detection in a reconfigurable platform for electronic system prototyping is proposed. It makes use of image processing techniques to first, extract pin core regions by a two-pass process: a top-down multi-level erosion process to remove touching parts of pin regions, followed by a bottom-up pin core recovery process to recover core regions removed by the first process. Once all pin cores have been isolated, regions associated to every pin can be determined by a simple segmentation procedure based on the shortest distance principle. The proposed approach has successfully extracted the pin maps from many circuit footprint images, even in cases of touching pin regions. The results produced by the proposed method have also been compared with those obtained from the reference Watershed algorithm and this shows that our approach provides better results in terms of pin recovery and pin positioning accuracy for the type of images produced by our electronic prototyping system.

This paper presents a framework for the automatic creation of netlists for arbitrary electronic circuits. The methodology relies on defining interfaces that allow a set of integrated circuits and other electronic components to be interconnected without user intervention. The framework, called "Intelligent Netlist Creator", has been successfully tested on several circuits. The results show that the proposed flow for netlist creation assists the user by automating some connections whenever possible.

A recently proposed rapid prototyping technology for electronic systems, which is based on a WSI active configurable circuit board comprising more than one million contact, can be programmed to interconnect integrated circuit packages deposited on its surface. This technology has some similarities, but also some key distinctive constraints when compared to conventional printed circuit boards. A workflow that supports the design with such configurable circuit boards is proposed. As part of this workflow, algorithms and tools for package recognition and for routing through a multi-dimensional mesh interconnection network is proposed and implemented. Results reported in this paper confirm the feasibility of the proposed workflow and several architectural choices made with respect to the configurable circuit board technology. Using the prototype tools reported in this paper, packages are successfully recognized and netlists are routed even though they use up to 50% of the contact point resources, which corresponds to an extremely dense circuit board.

A reformulated Adaptive Resonance Theory (ART) neural network algorithm has recently been implemented in digital hardware. Naturally, the fixed point, fixed word length data format used causes some output differences with respect to floating point computer simulation. These differences are observed when using realistic input data. The effects of input quantization and the accumulation of round off errors in the arithmetic operations making up the algorithm are analyzed. Even a small quantization or round off error can trigger a change in the clustering produced. This does not mean that the clustering is not valid. Indeed, the validity of the clustering can be comparable to that obtained by floating point computer simulation, provided the word length is sufficient. This is verified on realistic input data consisting of radar pulses received from a number of emitters.

The paper analyzes the performance differences found between software and hardware/sofware implementations of a reformulated fuzzy ART neural network algorithm. This reformulated algorithm is a solution for a real time radar signal clustering problem. The software implementations run on a 50 MHz TMS320C40 DSP, and the hardware/sofware implementation runs on the same DSP for its software part, whereas the FPGA based application specific hardware accelerator is realized on MiroTech's X-CIM TIM40 module. This investigation of FPGA based acceleration gave excellent results for our application: acceleration factors up to 68.9 have been reached.

In this paper, we examine the impact of using the hierarchy of the design and multiple delay models defined at different abstraction levels to speed up the timing performance evaluation of VLSI circuits. The algorithms implemented in the Dynamic and Hierarchical Timing Analysis (DHTA) tool are described. DHTA rapidly identifies the critical portions of the circuit at high hierarchical levels with rough delay models. These portions are then successively studied at more detailed levels for maximal accuracy. The effects on processing time of exploiting the design hierarchy and using several delay models are characterized. The implementation of DHTA demonstrates experimentally the benefits of using a mixed-mode approach for timing analysis. We show that considering all available hierarchical levels may degrade the computing time and heuristics are proposed to select the hierarchical levels which generally lead to a speed-up.