The latest design specs have arrived and it is now clear that timing runs will not fit in our machines. What to do! Is hierarchical STA the perfect solution? Will it work exactly like flat? How will it interact with the hierarchical design implementation? This talk will present the advantages and limitations of using hierarchical STA and how it impacts the design process.

In multiple input switching (MIS) analysis, input signal alignment is one of the key factors which determines the quality and the accuracy of the approach. In this paper, we propose a new signal alignment methodology for MIS analysis based on a transistor level simulator at the core of the static timing analysis. Our proposed methodology searches through the possible input vectors in an efficient order to reduce the number of simulations and finds a true worst case signal alignment for both the MIN and the MAX analysis. In our 180 nm simulation setup, the worst-case delay is predicted within 0.5% error for more than 97% of test cases performing an average of less than two simulations per logic gate.

Ignoring the effect of simultaneous switching for logic gates causes silicon failures for high performance microprocessor designs. The main reason to omit this effect is the run time penalty and potential over-conservatism. Run times are directly proportional to the vector sizes. Efficient algorithms are presented that prune the multiple input switching (MIS) vector set to a worst-case covering using a boolean logic abstraction of the gate. This non-physical representation reduces the vector size to approximately n vectors for an n-input gate. This is effectively the same vector set size as the optimal single input switching vector set. There are no errors for 88 % the simulations using a Monty-Carlo coverage on a 90nm static library, and the magnitude of the errors are less than 5 % on average. 1.

Capturing RLCK circuit responses accurately with existing model order reduction (MOR) techniques is very expensive. Direct metrics for fast analysis of RC circuits exist but there is no such technique for RLCK circuits. This paper introduces a new family of MOR techniques based on piece-wise functions to capture RLCK circuit responses accurately using only four or five moments. The time-domain response is approximated using a piece-wise function whose pieces are simple polynomials. The proposed method is fast and guaranteed stable and it avoids the calculation of poles and residues associated with existing model order reduction techniques. Results for many different industrial netlists indicate that delay and transition time can be captured within 5% error using only four moments. To the authors' knowledge, there is no existing method that can extract as much information about RLCK circuits with only four or five moments.

With an increasing trend in the variation of the primary parameters affecting circuit performance, the need for statistical static timing analysis (SSTA) has been firmly established in the last few years. While it is generally accepted that a timing analysis tool should handle parameter variations, the benefits of advanced SSTA algorithms are still questioned by the designer community because of their significant impact on complexity of STA flows. In this paper, we present convincing evidence that a path-based SSTA approach implemented as a post-processing step captures the effect of parameter variations on circuit performance fairly accurately. On a microprocessor block implemented in 90nm technology, the error in estimating the standard deviation of the timing margin at the inputs of sequential elements is at most 0.066 FO4 delays, which translates in to only 0.31% of worst case path delay.

The new technique of time shifted moment matching (TSMM) is introduced in this paper. The TSMM technique performs moment matching (for expansion around s = 0) on a time-shifted version of the original signal. As compared to other well-known techniques (such as AWE by Pillage and Rohrer, 1990), TSMM offers distinct advantages. The 50% delay and rise time are determined with much more accuracy for a given approximation order. Moreover, the solutions have significantly improved accuracy as compared to AWE, especially for moderate to highly inductive signals. TSMM is able to achieve the approximation capability of PVL (Feldmann and Freund, 1995) and PRIMA (Odabasioglu et al., 1998) with much lower approximation order.

Current complimentary metal-oxide-semiconductor technologies are characterized by interconnect lines with increased relative resistance with respect to driver output resistance. Designs generate signal waveshapes that are very difficult to model using a single-parameter model such as the transition time. In this paper, we present a simple and robust two-parameter analytical expression for waveform modeling based on the Weibull cumulative distribution function. The Weibull model accurately captures the variety of waveshapes without introducing significant runtime overhead and produces results with less than 5% error. We also present a fast and simple algorithm to convert waveforms obtained by circuit simulation to the Weibull model. A methodology for characterizing gates for the new model is also presented. Simulation results for many single- and multiple-input gates show errors well below 5%. Our model can be used in a mixed environment where some signals may still be characterized by a single parameter.

There is an increased dominance of intra-die process variations, creating a need for an accurate and fast statistical timing analysis. Most of the recent proposed approaches assume a Single Input Switching model. Our experiments show that SIS underestimates the mean delay of a stage by upto 20% and overestimates the standard deviation upto 26%. We also show that Multiple Input Switching has a greater impact on statistical timing, than regular static timing analysis. Hence, we propose a modeling technique for gate delay variability, considering MIS. Our model can be efficiently incorpo-rated into most of the statistical timing analysis frameworks. On average over all test cases, our approach underestimates mean delay of a stage by 0.01% and overestimates the standard deviation by only 2%, hence increasing the robustness to process variations. Our modeling technique is independent of the deterministic MIS model, and we show that its sensitivity to variations in the MIS model is small.

Unbuffered latches are often used in high-performance designs with custom timing flows. Adding these circuits to a standard library enables improved designs without blowing the library size. We observe a high potential frequency gain (up to 16%) for smaller power consumption. Accurate models for static timing analysis are required to reach a good point on the safety to performance trade-off. We are proposing a complete modeling methodology that can fit in a standard timing analysis flow. An accurate n-model is presented for the input impedance of an unbuffered latch with less than 2% error. We also present a new setup criteria required for these latches. We also show that more advanced waveform models are required to model the output. A Weibull waveform model proves to be effective in this case.

Computing the noise on delay effects is required for all circuits from simple ASIC designs to microprocessors. Transistor-level simulation engines make accurate delay calculation affordable only if the number of simulation per stage is very small. We propose a solution that predicts the alignment of aggressor signals with respect to the victim signal to induce the worst-case noise effect on delay. The aggressor alignment can be used to setup a detailed simulation. The worst-case delay in the presence of noise is predicted within 5% error for more than 99% of the cases tested using an average of 1.27 simulations per stage transition.

Static timing analysis breaks down the longest path problem into waveform analysis of paths of logic stages that are comprised of nonlinear transistors and complex RLC loads. Runtime efficiency is of the utmost importance; however, the waveform evaluation of these logic stages cannot be accelerated via timing simulation algorithms that attempt to exploit temporal or spatial latency since the simulation problem is already a partitioned one. TETA was developed as a general purpose transistor-level waveform evaluation engine for providing accuracy-efficiency tradeoffs for these logic-stage waveform evaluation problems that are encountered during timing analysis. Of particular emphasis are the large RC(L) coupled logic stages which present the bottleneck for waveform evaluation along multiple stages of a digital circuit path. TETA applies a novel compaction scheme for the logic-stage transistor clusters and employs a novel nonlinear algebraic solution method to analyze the circuit. Importantly, stability of the waveform evaluation with TETA requires only stable single-input multi-output N-port interconnect models that are not necessarily passive. Waveform evaluators that use general transistor and piecewise linear device models require provably passive multi-input multi-output interconnect models that can be extremely inefficient for large coupled N-port problems. Furthermore, the methodology in TETA brings extra efficiency by avoiding extra matrix factorizations and enabling the use of device model tables without any loss of accuracy. Complex logic gates and nonlinear capacitors are handled without loss of generality.

TETA is an interconnect-centric waveform calculator that was optimized to achieve the utmost efficiency for analyzing logic stages comprised of transistors and large coupled RC(L) interconnect models. TETA applies a novel compaction for the transistor clusters and employs successive chord iterations to solve the resulting nonlinear equations. These algorithms permit the use of simple SIMO (single input multi-output) N-port interconnect models since macromodel passivity is not required. The successive chord analysis also enables TETA to avoid the N-port matrix factorization during nonlinear iterations and allows the use of simple table look-up models for MOS devices. Complex gates and nonlinear capacitors can be handled without loss of generality.

In this paper we develop a gate level model that allows us to determine the best and worst case delay when there is dominant interconnect coupling. Assuming that the gate input windows of transition are known, the model can predict the worst and best case noise, as well as the worst and best case impact on delay. This is done in terms of a Ceff based gate model under general RC interconnect loading conditions. I. INTRODUCTION As IC dimensions scale to the deep submicron range, their multi-level interconnects are constructed such that the coupling capacitance becomes the dominant component of load capacitance. This effect is largely the result of the increased ratio between the lateral and the vertical capacitance of the line. The increased number of metal layers is the other source of coupling capacitance problems, since there is a reduced likelihood of a nearby "ground plan." The lateral capacitance is increased by the relative increase in the metal thickness with respect to line sp...

Gate and cell level timing analysis remains popular yet inherently incompatible with RC and RCL interconnect loads. The Ceff concept was proposed in Qian et. al. (1994) to model the interaction of empirical gate/cell delay models and RC loads. The most efficient Ceff model works in terms of precharacterizing the parameters of a time varying Thevenin voltage source model (in series with a fixed resistor) over a wide range of effective capacitance load values. In this paper we generalize this Thevenin equivalent Ceff model to enable future technologies which may include reduced supply voltages and RCL loads, without further complicating the Ceff algorithm or iterations.

Most timing simulators obtain their efficiency over circuit simulation in terms of explicit integration algorithms that have dif-ficulty handling the stiff RC circuit models which characterize interconnect-dominated paths. In this paper we describe a reduced-order N-port interconnect macromodel for timing simula-tion. This macromodel is shown to improve the timing simulation efficiency dramatically since it alleviates the stiff circuit problem. Moreover, through its compatibility with the simple timing simula-tion transistor models, it is shown that this macromodel does not suffer from the dramatic increase in complexity with an increase in the number of ports like circuit simulation. I.

Due to its simplicity, the ubiquitous Elmore delay, or first moment of the impulse response, has been an extremely popular delay metric for analyzing RC trees and meshes. Its inaccuracy has been noted however and it has been demonstrated that higher order moments can be mapped to dominant pole approximations (e.g. AWE) in the general case. The first three moments can be mapped to a two pole approximation, but stability is an issue and even a stable model results in a transcendental equation that must be iteratively evaluated to determine the delay. We describe an explicit delay approximation based on the first three moments of the impulse response. We begin with the development of a provably stable two pole transfer function/impedance model based on the first three moments (about s=0) of the impulse response. Then, since the model form is known, we evaluate the delay (any waveform percentage point) in terms of an analytical approximation that is consistently within a fraction of 1 percent of the exact solution for this model. The result is an accurate, explicit delay expression that will be an effective metric for high speed interconnect circuit models.

For efficiency, the performance of digital CMOS gates is often expressed in terms of empirical models. Both delay and short-circuit power dissipation are sometimes characterized as a function of load capacitance and input signal transition time. However, gate loads can no longer be modeled by purely capacitive loads for high performance CMOS due to the RC metal interconnect effects. This paper presents a methodology for interfacing empirical gate models to reduced order RC interconnect models in terms of a nonlinear iteration procedure. The delay and power are calculated with errors on the same order as those for the original empirical equations. Moreover, a linear equivalent gate model is generated which accurately captures the delays at the interconnect fan-out nodes.

As signal speeds increase and gate delays decrease for high-perform ance digital integrated circuits, the gate delay m odeling problem becom es increasingly m ore difficult.With scaling, increasing interconnect resistances and decreasing gateoutput im pedances m ake it m ore difficult to em pirically characteriz e gate-delay m odels.Moreover, the single-input-switching assum ption for the em pirical m odels is incom patible with the inevitable sim ultaneous switching for todays high-speed logic paths.In this paper a new em pirical gate delay m odel is proposed.Instead of building the em pirical equations in term s of capacitance loading and input-signal transition tim e, the m odels are generated in term s of param eters which com bine the benefits of em pirically derived k -factor m odels and switch-resistor m odels to efficiently: 1) handle capacitance shielding due to m etal interconnect resistance, 2) m odel the RC interconnect delay, and 3) provide tighter bounds for sim ultaneous switching.