Quantum computers will be a revolutionary extension of the heterogeneous computing world. They consist of many quantum bits (qubits) and require a careful design of the interface between the classical computer architecture and the quantum processor. For example, even single nanosecond variations of the interaction may have an influence on the quantum state. Designing a tailored interface electronics is therefore a major challenge, both in terms of signal integrity with respect to single channels, as well as the scaling of the signal count. We developed such an interface electronics, an RFSoC-based qubit control system called QiController. In this article, we present the modular FPGA firmware design of our system. It features so-called digital unit cells, or QiCells. Each cell contains all the logic necessary to interact with a single superconducting qubit, including a custom-built RISC-V-based sequencer. Synchronization and data exchange between the cells is facilitated using a special star-point structure. Versatile routing and frequency-division multiplexing of generated signals between QiCells and converters are also supported. High-level programmability is provided using a custom Python-based description language and an associated compiler. We furthermore provide the resource utilization of our design and demonstrate its correct operation using an actual superconducting five-qubit chip.

Quantum computers will be a revolutionary extension of the heterogeneous computing world. They consist of many quantum bits (qubits) and require a careful design of the interface between the classical computer architecture and the quantum processor. Even single nanosecond variations of the interaction may have an influence on the quantum state. In this paper, we present the modular design of the FPGA firmware which is part of our qubit control electronics. It features so-called digital unit cells where each cell contains all the logic necessary to interact with a single superconducting qubit. The cell includes a custom-built RISC-V-based sequencer, as well as two signal generators and a signal recorder. Internal communication within the cell is handled using a modified Wishbone bus with custom 2-to-N interconnect and deterministic broadcast functionality. We furthermore provide the resource utilization of our design and demonstrate its correct operation using an actual superconducting five qubit chip.

Suitable techniques for reading out large arrays of metallic magnetic calorimeters are very challenging and demand optimal performance in each system stage to preserve intrinsic fast signal rise time, excellent energy resolution, large energy dynamic range, and highly linear detector response. A multiplexer based on superconducting quantum interference device is the key component in achieving this goal. Linearity of the response requires a technique called flux-ramp modulation, which generates a phase-modulated complex waveform according to the sensor signal. At the end-cap of the signal processing chain it is currently recovered by a demodulation process referred to as Fourier measurement. In this letter, we prove that the mentioned method is equivalent to a maximum likelihood estimation, build an analogy to the sensor array-based direction of arrival estimation, propose an alternative approach based on the eigenvalue decomposition of a correlation matrix, present the mathematical formulation, discuss the results, and compare both methods. Our method is robust against transients due to flux ramp returning point and allows proper estimation in large phase ranges.

The Compact Muon Solenoid (CMS) experiment at CERN is scheduled for a major upgrade in the next decade in order to meet the demands of the new High Luminosity Large Hadron Collider. Amongst others, a new tracking system is under development including an outer tracker capable of rejecting low transverse momentum particles by looking at the coincidences of hits (stubs) in two closely spaced sensor layers in the same tracker module. Accepted stubs are transmitted off-detector for further processing at 40 MHz. In order to maintain under the increased luminosity the Level-1 trigger rate at 750 kHz, tracker data need to be included in the decision making process. For this purpose, a system architecture has to be developed that will be able to identify particles with transverse momentum above 3 GeV/c by building tracks out of stubs, while achieving an overall processing latency of maximum 4us. Targeting these requirements the current paper presents an FPGA-based track finding architecture that identifies track candidates in real-time and bases its functionality on a fully time-multiplexed approach. As a proof of concept, a hardware system has been assembled targeting the MP7 MicroTCA processing card that features a Xilinx Virtex-7 FPGA, demonstrating a realistic slice of the track finder. The paper discusses the algorithms' implementation and the efficient utilisation of the available FPGA resources, it outlines the system architecture, and presents some of the hardware demonstrator results.

For almost any electronic system, simulation at an early stage of development is essential. This is even more important for large systems. While SystemC is well suited for simulations of large systems on a high abstraction level, it provides only limited functionality to model large regular structures -- structures that consist of the same elements. The library presented in this paper provides a container that helps build up, configure and access such structures for SystemC simulations. Fewer lines of code need to be written to achieve the same result, which reduces the time needed for system modeling and the number of errors. By applying the library to a system-level simulation of the Compact Muon Solenoid (CMS) Track Trigger, an extreme, heterogeneous embedded systems by any standards, the usefulness of the library has been proved.

Design complex embedded systems demands method and tools that allow the simulation and verification in an efficient and practical way. This paper proposes the development and evaluation of a distributed simulation platform of heterogeneous simulators based on High Level Architecture (HLA), a middleware for distributed discrete event simulation, in order to create an environment with high-performance execution of large-scale, heterogeneous and complex embedded systems. However, integrate hybrid systems is not trivial, because there is no guarantee that two systems that perfectly work separately will work well together. Experimental results of five different scenarios are presented, which integrate five different simulations tools: Ptolemy II, SystemC, Omnet++, Veins, Stage (a Robot Operating System compatible simulator) and physical robots. The experiments show success in application of Wireless Sensor Networks (WSN), power estimation of circuit design, robotic simulation and co-simulation of real robots.

Embedded systems are steadily growing in complexity and nowadays power consumption additionally plays an important role. Designing and exploring such systems embedded in its environment demand for holistic and efficient simulations. In this work we use a simulation framework based on the HLA (High-Level Architecture) and the modeling tool Ptolemy II to enable complex heterogeneous distributed simulations of embedded systems. In this context, we introduce a co-simulation based power estimation approach by integrating domain-specific simulators as well as off-the-shelf HDL simulator and synthesis tools. This enables cross-domain interaction and generation of realistic on-the-fly stimuli data for Register Transfer Level and Gate Level models as well as the gathering of power estimation data. We apply the framework to a Vehicle-2-X scenario evaluating an ECDSA signature processing core which ensures trustworthiness in vehicular wireless networks. To evaluate dynamic power reduction possibilities on application level we additionally introduce a V2X Message Evaluation technique to reduce signature verification efforts. It shows how realistic on-the-fly stimuli data obtained by the framework can improve the exploration and estimation of dynamic power consumption.

Electric/Electronic architectures in modern automobiles evolve towards an hierarchical approach where functionalities from several ECUs are consolidated into few domain computers. Performance requirements directly lead to multicore solutions but also to a combination of very different requirements on such ECUs. Using virtualization in addition is one promising way of achieving segregation in time and space of shared resources. Based on examples taken from the automotive domain several concepts for efficient hardware extensions of coprocessors and I/O devices are shown in this contribution. These provide mechanisms to ensure quality of service (QoS) levels in terms of execution time, throughput and latency. The resulting infotainment architecture is a feasibility study and is integrated into a vehicle demonstrator as centralized infotainment platform (VCT).

Within this paper an adaptive approach for parallel simulation of SystemC RTL models on future many-core architectures like the Single-chip Cloud Computer (SCC) from Intel is presented. It is based on a configurable parallel SystemC kernel that preserves the partial order defined by the SystemC delta cycles while avoiding global synchronization as far as possible. The underlying algorithm relies on a classification of existing communication relations between parallel processes. The type and topology of communication relations determines the type and number of causality conditions that need to be fulfilled during runtime. The parallel kernel is complemented by an automated tool flow that allows detecting relevant model-specific properties, performing a fine-grained model partitioning, classifying communication relations and configuring the kernel. Experiments by means of a MPSoC model show, that pure local synchronization can provide significant performance gains compared to global synchronization. Furthermore, the combination of local synchronization with fine-grained partitioning provides additional degrees of freedom for optimization.

Especially in complex system-of-systems scenarios, where multiple high-performance or real-time processing functions need to co-exist and interact, reconfigurable devices together with virtualization techniques show considerable promise to increase efficiency, ease integration and maintain functional and non-functional properties of the individual functions. In this paper, we propose a flexible interface architecture with low overhead for coupling reconfigurable coprocessors to high-performance general-purpose processors, allowing customized yet efficient construction of heterogeneous processing systems. Our implementation is based on PCI Express (PCIe) and optimized for virtualized systems, taking advantage of the SR-IOV capabilities in modern PCIe implementations. We describe the interface architecture and its fundamental technologies, detail the services provided to individual coprocessors and accelerator modules, and quantify key corner performance indicators relevant for virtualized applications.

Nowadays, embedded systems have a huge amount of computational power and consequently, high complexity. It is quite usual to find different applications being executed in embedded systems. Embedded system design demands for method and tools that allow the simulation and verification in an efficient and practical way. This paper proposes the development and evaluation of a solution for embedded modeling and simulation of heterogeneous Models of Computation (MoCs) in a distributed way by the integration of Ptolemy II and the High Level Architecture (HLA), a middleware for distributed discrete event simulation, in order to create an environment with high-performance execution of large-scale heterogeneous models. Experimental results demonstrate, that the use of a non distributed simulation for some situations can be infeasible, as well as the use of distributed simulation with few machines, like one, two or three computers. It was demonstrated that a speedup of factor 4 was acquired when a model with 4,000 thousands actors were distributed in 8 different machines.

This paper introduces the first available tool flow for Dynamic Partial Reconfiguration on the Spartan-6 family. In addition, the paper proposes a new configuration method called Fast Start-up targeting modern FPGA architectures, where the FPGA is configured in two-steps, instead of using a single (monolithic) full device configuration. In this novel approach, only the timing-critical modules are loaded at power-up using the first high-priority bitstream, while the non-timing critical modules are loaded afterwards. This two-step or prioritized FPGA start-up is used in order to meet the extremely tight startup timing specifications found in many modern applications, like PCI-express or automotive applications. Finally, the developed tool flow and methods for Fast Start-up have been used and tested to implement a CAN-based automotive ECU on a Spartan-6 evaluation board (i.e., SP605). By using this novel approach, it was possible to decrease the initial bitstream size and hence, achieve a configuration time speed-up of up to 4.5×, when compared to a standard configuration solution.

In this paper we present an optically powered and motorized video camera system. Energy for the camera sensor is supplied by a glass fiber carrying 800 mW of optical power, which the sensor converts back to 320 mW of electrical power. The specific advantage of this arrangement is galvanic isolation and a very high robustness with respect to electromagnetic interference. We demonstrate that sufficient energy can be transmitted for driving an Actel Igloo FPGA, which performs the necessary signal processing. Additionally, with the help of capacitive energy storage, some small actuators can be supplied which move the camera sensor head. The base station of the system, based on a Xilinx Virtex-5 FPGA, holds a LEON-3 based system-on-chip encoding the incoming VGA video stream into Motion-JPEG formatted data in realtime, which may be directly sent to the internet using an Ethernet interface. The prototype has numerous fields of application where it performs much better than stateof-the-art solutions. Most prominent examples are visual sensors in high voltage areas as well as medical endoscopes.

MOTIVATION: In life sciences, interpretability of machine learning models is as important as their prediction accuracy. Linear models are probably the most frequently used methods for assessing feature relevance, despite their relative inflexibility. However, in the past years effective estimators of feature relevance have been derived for highly complex or non-parametric models such as support vector machines and RandomForest (RF) models. Recently, it has been observed that RF models are biased in such a way that categorical variables with a large number of categories are preferred. RESULTS: In this work, we introduce a heuristic for normalizing feature importance measures that can correct the feature importance bias. The method is based on repeated permutations of the outcome vector for estimating the distribution of measured importance for each variable in a non-informative setting. The P-value of the observed importance provides a corrected measure of feature importance. We apply our method to simulated data and demonstrate that (i) non-informative predictors do not receive significant P-values, (ii) informative variables can successfully be recovered among non-informative variables and (iii) P-values computed with permutation importance (PIMP) are very helpful for deciding the significance of variables, and therefore improve model interpretability. Furthermore, PIMP was used to correct RF-based importance measures for two real-world case studies. We propose an improved RF model that uses the significant variables with respect to the PIMP measure and show that its prediction accuracy is superior to that of other existing models. AVAILABILITY: R code for the method presented in this article is available at http://www.mpi-inf.mpg.de/ approximately altmann/download/PIMP.R CONTACT: [email protected], [email protected] SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.

We present an application tailored packed-based SoC communication system with one-hop communication between all entities, priority-based arbitration, broadcast and multicast support on a bus-shaped basis. It is located as a hybrid between NoC and bus approaches, closing the gap for mostly streaming-based systems with the need for highly flexible communication patterns and multicast messages that are below a certain size. The system is implemented and evaluated on a FPGA within a car-to-car communication gateway application.

Vehicle-to-vehicle communication (V2VC) promises to be a next major step towards safe and efficient road traffic. This contribution presents a V2V communication system on FPGA-basis. It provides a flexible and modular hardware framework for various software-implemented V2V applications and routing algorithms. Exploiting the benefits of reconfigurable hardware the system manages to provide hardware acceleration for security processing and data preprocessing while at the same time being adaptive to traffic situations, different environment and evolving standards and applications. We present the overall structure of the system, detail modules and communication system and present special mechanisms used to exploit FPGA benefits. Finally we give results concerning performance values and resource usage.

A Hardware/Software Codesign approach based on a MicroBlaze softcore processor and a GF2n-coprocessor module to form a minimal hardware architecture for HECC on low-cost Xilinx FPGAs is described in this paper. Exploiting the features of the MicroBlaze's integrated interfaces instructions are streamed on-demand to the coprocessor to keep the controlflow highly flexible. At the same time the dataflow between hardware and software is minimized. Comparison with previous architectures shows high acceleration of HECC with minor increase in hardware resources. It is demonstrated that this speed-up can be used for countermeasures on algorithmic level against basic side-channel attacks while still keeping real-time constraints.

To get more information about oncoming road and traffic situations, exchange of data between cars is a large benefit. But relying on data obtained from other cars and hence sensors not under direct control of the system, guaranteeing trustworthiness and integrity of this data is of paramount importance. This creates the need for security measures for the data exchange which impose high computational demands to achieve the low latencies needed for safety applications. In this contribution we present a hardware security module allowing efficient calculation and verification of signatures. Implementation as well as integration aspects are being discussed in this paper.

For improving the security of embedded systems, trusted computing is a promising technology. For the area of microprocessors in general and personal computers in particular the Trusted Computing Group (TCG) has published detailed specifications. The resulting hardware has been available for some years. This contribution discusses the feasibility of deploying ideas from trusted computing in the domain of reconfigurable hardware, esp. FPGAs, and possible benefits and drawbacks. We give a proposal to use actually available FPGA technology to build a trusted platform on reconfigurable hardware. We also show how trusted computing can deal with partial dynamic reconfiguration while still allowing the user to fully exploit its potentials.

In todays and future automotive electric/electronic architectures the central gateway is one of the key components. The introduction of high performance bus systems like FlexRay and Ethernet, as well as new applications, creates additional requirements for gateway systems. The usage of reconfigurable hardware gives an interesting alternative to existing microcontroller based solutions. A modular gateway prototype based on a field programmable gate array (FPGA) with specialized routing modules allows a significant speed up compared to microcontroller solutions. The architecture of the routing hardware modules as well as the most relevant implementation details are described in this paper. The complete routing functionality was implemented and tested under series constraints. A performance comparison shows significant speedups. Our toolflow for routing table generation is presented in addition. A final version of the gateway has been successfully integrated into a modern mid class vehicle.

Innovation in today's automobiles is mainly driven by electronic development. Standard infotainment devices delivered by car manufacturers offer services such as navigation, television, DVD, telephony and more. Especially in the last few years a trend can be recognized extending from these OEM specific solutions towards integration of consumer electronic devices such as iPods, cell phones or the like. An approach solely based on software adjustments might not be sufficient to solve the problem of car to mobile device communication. Reconfigurable hardware offers a unique possibility of adapting to a given problem in hardware as well as software structures. The feature of partial dynamic reconfiguration in particular can contribute significantly to the flexibility of the overall system. Any adaptation of the running system should be automatic and going unnoticed by the user. This contribution depicts an approach that utilizes reconfigurable hardware for connecting consumer electronics to an automobile. Detection of protocols, loading of appropriate hardware interfaces, as well as integration of offered or requested services are the essential steps presented in this paper.

We assess the variability of protein function in protein sequence and structure space. Various regions in this space exhibit considerable difference in the local conservation of molecular function. We analyze and capture local function conservation by means of logistic curves. Based on this analysis, we propose a method for predicting molecular function of a query protein with known structure but unknown function. The prediction method is rigorously assessed and compared with a previously published function predictor. Furthermore, we apply the method to 500 functionally unannotated PDB structures and discuss selected examples. The proposed approach provides a simple yet consistent statistical model for the complex relations between protein sequence, structure, and function. The GOdot method is available online (http://godot.bioinf.mpi-inf.mpg.de).

MOTIVATION: An approach for identifying similarities of protein-protein binding sites is presented. The geometric shape of a binding site is described by computing a feature vector based on moment invariants. In order to search for similarities, feature vectors of binding sites are compared. Similar feature vectors indicate binding sites with similar shapes. RESULTS: The approach is validated on a representative set of protein-protein binding sites, extracted from the SCOPPI database. When querying binding sites from a representative set, we search for known similarities among 2819 binding sites. A median area under the ROC curve of 0.98 is observed. For half of the queries, a similar binding site is identified among the first two of 2819 when sorting all binding sites according the proposed similarity measure. Typical examples identified by this method are analyzed and discussed. The nitrogenase iron protein-like SCOP family is clustered hierarchically according to the proposed similarity measure as a case study. AVAILABILITY: Python code is available on request from the authors.

HIV-1 cell entry commonly uses, in addition to CD4, one of the chemokine receptors CCR5 or CXCR4 as coreceptor. Knowledge of coreceptor usage is critical for monitoring disease progression as well as for supporting therapy with the novel drug class of coreceptor antagonists. Predictive methods for inferring coreceptor usage based on the third hypervariable (V3) loop region of the viral gene coding for the envelope protein gp120 can provide us with these monitoring facilities while avoiding expensive phenotypic tests. All simple heuristics (such as the 11/25 rule) as well as statistical learning methods proposed to date predict coreceptor usage based on sequence features of the V3 loop exclusively. Here, we show, based on a recently resolved structure of gp120 with an untruncated V3 loop, that using structural information on the V3 loop in combination with sequence features of V3 variants improves prediction of coreceptor usage. In particular, we propose a distance-based descriptor of the spatial arrangement of physicochemical properties that increases discriminative performance. For a fixed specificity of 0.95, a sensitivity of 0.77 was achieved, improving further to 0.80 when combined with a sequence-based representation using amino acid indicators. This compares favorably with the sensitivities of 0.62 for the traditional 11/25 rule and 0.73 for a prediction based on sequence information as input to a support vector machine and constitutes a statistically significant improvement. A detailed analysis and interpretation of structural features important for classification shows the relevance of several specific hydrogen-bond donor sites and aliphatic side chains to coreceptor specificity towards CCR5 or CXCR4. Furthermore, an analysis of side chain orientation of the specificity-determining residues suggests a major role of one side of the V3 loop in the selection of the coreceptor. The proposed method constitutes the first approach to an improved prediction of coreceptor usage based on an original integration of structural bioinformatics methods with statistical learning.

BACKGROUND: In recent years protein structure prediction methods using local structure information have shown promising improvements. The quality of new fold predictions has risen significantly and in fold recognition incorporation of local structure predictions led to improvements in the accuracy of results. We developed a local structure prediction method to be integrated into either fold recognition or new fold prediction methods. For each local sequence window of a protein sequence the method predicts probability estimates for the sequence to attain particular local structures from a set of predefined local structure candidates. The first step is to define a set of local structure representatives based on clustering recurrent local structures. In the second step a discriminative model is trained to predict the local structure representative given local sequence information. RESULTS: The step of clustering local structures yields an average RMSD quantization error of 1.19 A for 27 structural representatives (for a fragment length of 7 residues). In the prediction step the area under the ROC curve for detection of the 27 classes ranges from 0.68 to 0.88. CONCLUSION: The described method yields probability estimates for local protein structure candidates, giving signals for all kinds of local structure. These local structure predictions can be incorporated either into fold recognition algorithms to improve alignment quality and the overall prediction accuracy or into new fold prediction methods.

BACKGROUND: In the area of protein structure prediction, recently a lot of effort has gone into the development of Model Quality Assessment Programs (MQAPs). MQAPs distinguish high quality protein structure models from inferior models. Here, we propose a new method to use an MQAP to improve the quality of models. With a given target sequence and template structure, we construct a number of different alignments and corresponding models for the sequence. The quality of these models is scored with an MQAP and used to choose the most promising model. An SVM-based selection scheme is suggested for combining MQAP partial potentials, in order to optimize for improved model selection. RESULTS: The approach has been tested on a representative set of proteins. The ability of the method to improve models was validated by comparing the MQAP-selected structures to the native structures with the model quality evaluation program TM-score. Using the SVM-based model selection, a significant increase in model quality is obtained (as shown with a Wilcoxon signed rank test yielding p-values below 10(-15)). The average increase in TMscore is 0.016, the maximum observed increase in TM-score is 0.29. CONCLUSION: In template-based protein structure prediction alignment is known to be a bottleneck limiting the overall model quality. Here we show that a combination of systematic alignment variation and modern model scoring functions can significantly improve the quality of alignment-based models.

UNLABELLED: ROCR is a package for evaluating and visualizing the performance of scoring classifiers in the statistical language R. It features over 25 performance measures that can be freely combined to create two-dimensional performance curves. Standard methods for investigating trade-offs between specific performance measures are available within a uniform framework, including receiver operating characteristic (ROC) graphs, precision/recall plots, lift charts and cost curves. ROCR integrates tightly with R's powerful graphics capabilities, thus allowing for highly adjustable plots. Being equipped with only three commands and reasonable default values for optional parameters, ROCR combines flexibility with ease of usage. AVAILABILITY: http://rocr.bioinf.mpi-sb.mpg.de. ROCR can be used under the terms of the GNU General Public License. Running within R, it is platform-independent. CONTACT: [email protected].

We discuss possible algorithms for interpolating data given in a set of curves and/or points in a surface in /spl Ropf//sup 3/. We propose a set of basic assumptions to be satisfied by the interpolation algorithms which lead to a set of models in terms of possibly degenerate elliptic partial differential equations. The absolute minimal Lipschitz extension model (AMLE) is singled out and studied in more detail. We show experiments illustrating the interpolation of data on the sphere and the torus.