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Yung-Syau Chen

dblp:09/3342 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1991
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 87% Parallel and multicore computing · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Memory systems
cache coherence
0.011991
Delayed consistency and its effects on the miss rate of parallel programs · SC 1991
Memory systems › cache coherence
false sharing
0.011991
Delayed consistency and its effects on the miss rate of parallel programs · SC 1991
Parallel and multicore computing › parallel computing
parallel application performance
0.011991
Delayed consistency and its effects on the miss rate of parallel programs · SC 1991

Methods — techniques the papers use, named apart from their topics

execution-driven simulation · 0.0
YearPublicationVenuePosition
1991 Delayed consistency and its effects on the miss rate of parallel programs
abstract
In cache based multiprocessors a protocol must maintain coherence among replicated copies of shared writable data. In delayed consistency protocols the effect of out-going and in-coming invalidations or updates are delayed. Delayed coherence can reduce processor blocking time as well as the effects offalse sharing. In this paper, we introduce several implementations of delayed consistency for cache-based systems in the framework of a weakly­ ordered consistency model. A performance comparison of the delayed protocols with the corre sponding On-the-Fly (non-delayed) consistency protocol is made, through execution-driven simulations of four parallel algorithms. The results show that,for parallel programs in which false sharing is a problem, significant reductions in the data miss rate of paraUel programs can be obtained with just a small incre ase in the cost and complexity of the cache system.
Michel Dubois 0001, Jin-Chin Wang, Luiz André Barroso, Kangwoo Lee, Yung-Syau Chen
SC5