Major microprocessor vendors have integrated functional software-based self-testing in their manufacturing test flows during the last decade. Functional self-testing is performed by test programs that the processor executes at-speed from on-chip memory. Multiprocessors and multithreaded architectures are constantly becoming the typical general-purpose computing paradigm, and thus the various existing uniprocessor functional self-testing schemes must be adopted and adjusted to meet the testing requirements of complex multiprocessors. A major challenge in porting a functional self-testing approach from the uniprocessor to the multiprocessor case is to take advantage of the inherent execution parallelism offered by the multiple cores and the multiple threads in order to reduce test execution time. In this paper, we study the application of functional self-testing to chip multithreaded (CMT) processors. We propose a method that exploits thread-level parallelism (TLP) to speed up the execution of self-test routines in every physical core of a multiprocessor chip. The proposed method effectively splits the self-test routines into shorter ones, assigns the new routines to the hardware threads of the core and schedules their execution in order to minimize the core idle intervals due to cache misses or long latency operations and maximize the utilization of core computing resources. We demonstrate our method in the open-source CMT multiprocessor model, Sunpsilas OpenSPARC T1, which contains eight CPU cores, each one supporting four hardware threads. Our experimental results show a self-test execution speedup of more than three times compared to the single thread execution.

The higher complexity of the hardware and software employed by modern computing systems, as well as semiconductor technology scaling, are increasing the likelihood of Silent Data Corruption (SDC). SDC occurs when incorrect data is provided to the user, e.g., written to the memory or I/O system, and no error is triggered. Such events may have catastrophic effects, in the case of life critical applications, and represent a significant cost penalty for businesses. The purpose of this panel is to provide real examples of silent corruption, and discuss solutions for avoiding it. The presentations address SDC generated at the semiconductor device level, as well as the virtualization software level. Techniques for reducing SDC, from the circuit to system level, will be covered. Results of an extensive SDC study, carried out at Los Alamos National Laboratory (LANL) on high-performance computing (HPC) platforms are also given.

The third generation CMT (chip multithreaded) microprocessor from Sun Microsystems has 16 cores and is optimized for high throughput without compromising high single thread performance. This paper describes the unique challenges faced in DFX of this complex CMT processor and the DFX solutions deployed. Some of the notable new DFX features include a highly configurable scan architecture, a memory test network that leverages functional access paths, BIST of special memories, and a test mode for running functional tests in the presence of non-deterministic serdes interfaces. Identification of chips with partially good cores and caches is supported in manufacturing for yield and in the field for availability.

Silicon technology trends of 65nm technology and architectural trends of the next generation of processors, chip-sets and systems are driving new design paradigms and shifts in the approaches towards robust system design. This paper addresses the convergence of these trends in designing the next generation of highly reliable systems at Sun Microsystems.

The next generation of throughput computing systems designed by Sun Microsystems require interconnect with bandwidth of the order of Tbits/sec. Interconnect topologies for such high bandwidth are based on a few hundred SerDes I/Os on chips operating at multi-Gbps. Testing of these I/Os at only the component level is inadequate. In this paper, we describe the design-for-testability features for system manufacturing and on-line test of such I/Os and interconnect

Throughput computing requires chip I/O bandwidth of the order of Tbits/sec which can be met by high speed, large scale implementation of SerDes I/Os (serial/deserial differential I/Os with clock embedded in data stream). The traditional test philosophy and existing ATE do not meet the challenges of testing chip interfaces with few hundreds of I/Os operating at multi-Gbps. In this paper, we present the test challenges and describe on-chip DFT modes and new ATE directions for chip level characterization and test of such interfaces used in throughput computing chip sets

This paper presents an approach for analysis of system state differences observable through the scan chain for the debug of functional failures. A novel methodology for Latch Divergence Analysis (LDA) is proposed for creating stable failure signatures and reducing system noise. The methodology and processing flow have been integrated into the normal debug flow for the UltraSPARCTM family processors and have been successfully applied in numerous debugs in the bring-up of new products.

An emerging trend in microprocessor architecture for servers is to design chips with multiple processor cores on a chip called chip multi-processors (CMPs). Due to the short design cycle time and large size of these chips, the design-for-testability and testing of such chips is a major challenge. In this paper we describe a hierarchical DFT architecture for UltraSPARC/spl trade/ CMPs that is scalable with number of processor cores and can be implemented in a very short design cycle time. The DFT architecture allows testing of the processor cores individually for diagnosis as well as concurrently to reduce test application time and thus test cost. The DFT architecture can be easily ported across CMPs with different numbers of processor cores as well as to higher order CMPs designed by putting together CMPs.

The need for considering BIST requirements during the scheduling and assignment stages of behavioral synthesis has been demonstrated in previous research and techniques for reducing BIST resources of a data path during these stages of synthesis have been developed. However, the degree of freedom that can be exploited during scheduling and assignment to minimize these resources is often limited by the data and control dependencies of a behavior. In this paper, we propose transformation of a behavior before scheduling and assignment, namely introducing redundant computations such that the resulting data path is testable using few BIST resources. The transformation makes use of spare capacity of modules to add redundancy that enables test paths to be shared among the modules. A technique for identifying potential BIST resource sharing problems in a behavior and resolving them by redundant computations is presented. Introduiction of redundant computations is performed without compromising the latency and functional resource requirement of the behavior.

The degree of freedom that can be exploited during scheduling and assignment to minimize BIST resources is often limited by the data dependencies of a behavior. We propose transformation of a behavior by introducing redundant computations such that the resulting data path requires few BIST resources. The transformation makes use of sparecapacity of modules to add redundancy that enables test paths to be shared among the modules. A technique is presented for introducing redundant computations that reduce the BIST resource requirements of a data path without compromising the latency and functional resource constraints.

Built-in self-test (BIST) techniques modify functional hardware to give a data path the capability to test itself. The modification of data path registers into registers (BIST resources) that can generate pseudo-random test patterns and/or compress test responses, incurs an area overhead penalty. We show how scheduling and module assignment in high-level synthesis affect BIST resource requirements of a data path. A scheduling and module assignment procedure is presented that produces schedules which, when used to synthesize data paths, result in a significant reduction in BIST area overhead and hence total area.

Abstract|Lower bound estimations of resources at various stages of high-level synthesis are essential to guide synthesis algorithms towards optimal solutions.In this paper we present l o w er bounds on the number of test resources (i.e.test pattern generators, signature analyzers and CBILBO registers) required to test a synthesized data path using built-in self-test (BIST).The estimations are performed on scheduled data ow graphs and provide a practical way of selecting or modifying module assignments and schedules such that the resulting synthesized data path requires a small number of test resources to test itself.I.

Article Data path allocation for synthesizing RTL design with low BIST area overhead Share on Authors: Ishwar Parulkar Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CAView Profile , Sandeep Gupta Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CAView Profile , Melvin A. Breuer Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering - Systems, University of Southern California, Los Angeles, CAView Profile Authors Info & Claims DAC '95: Proceedings of the 32nd annual ACM/IEEE Design Automation ConferenceJanuary 1995 Pages 395–401https://doi.org/10.1145/217474.217561Online:01 January 1995Publication History 37citation177DownloadsMetricsTotal Citations37Total Downloads177Last 12 Months1Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

Article Free Access Share on Extraction of a high-level structural representation from circuit descriptions with applications to DFT/BIST Authors: Ishwar Parulkar Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CAView Profile , Melvin A. Breuer Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CA Department of Electrical Engineering Systems, University of Southern California, Los Angeles, CAView Profile , Charles A. Njinda Vertex Semiconductors, 1060, Rincon Circle, San Jose, CA Vertex Semiconductors, 1060, Rincon Circle, San Jose, CAView Profile Authors Info & Claims DAC '94: Proceedings of the 31st annual Design Automation ConferenceJune 1994 Pages 345–356https://doi.org/10.1145/196244.196417Online:06 June 1994Publication History 4citation145DownloadsMetricsTotal Citations4Total Downloads145Last 12 Months4Last 6 weeks0 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF