The objective here is to develop a uniform and comprehensive procedure for symbolic analysis of linear circuits using the Sum of the Tree Products (STP) of the circuit. We achieve this goal in two stages. In the first stage a circuit with active devices, such as VCCSs and I/O ports, is changed to a nullor circuit, i.e., to a circuit with only passive components and nullors. The nullor circuit is also partitioned into two parts, a passive circuit and an all-nullor circuit. It is shown that the magnitude of the STP, i.e., the determinant of the NAM, of the circuit is equal to the STP of the passive portion of the circuit, and the sign (0, 1, or −1) of the STP comes from its all-nullor part. Another significant development in this presentation is the replacement of the regular STP methodology with a rather new Admittance Method (AM). It is shown that by doing this the entire two-graph theory for active circuits as well as the use of 2-tree procedures for I/O ports analysis are eliminated. It is these new developments that substantially simplifies the circuit analysis and makes it quite efficient for symbolic representation of transfer functions.

This article has two objectives. The first one is to develop an Admittance Method (AM) for active circuits, which is a replacement for the Sum of the Tree Products (STP) used for symbolic analysis of circuits. A similar but very limited method is developed earlier (1976) for passive circuits. The second objective is to replace the active devices (mainly VCCS) in circuits with nullors, and prepare them for a smooth application of the AM. The method is replacing the well-known 2-graph methodology, and it is ideal for symbolic representation of circuits, especially for low component density. The core of the AM technique is based on parallel and series (P/S) operations that continuously combines the components until it is reduced to a single element. In case the P/S operations are exhausted but the circuit is still not a single element, we leave the P/S and remove as many elements from the circuit to regenerate new P/S operations. We continue it until the circuit terminates with a single element. It is shown that the admittance of the final element represents a port transfer function (admittance) with the numerator being the determinant of the Nodal Admittance Matrix (NAM). In case of active circuits, with gm, the method works when the dependent sources are replaced with nullors.

This article provides two new features that in combinations facilitate the construction of a transfer function in RC and RL circuits, and in s-expanded polynomials. First is the introduction of tuple-based array manipulations, where multiplications and divisions are replaced with convolutions and deconvolutions, respectively. Second, it introduces a new UaL decomposition for tuple-based matrices. The UaL decomposition is proven to be computationally more efficient compared to the traditional LU factorization. It is shown that the growth of the entries in both U and L matrices are gradual and follow a geometrical pattern, as the decomposition progresses. Another important feature of the UaL decomposition is that it does not generate nonzero remainders, or simply, it is “cancellation free”. The method is applied to the MNA representation of an RC (or RL) circuit. Finally, it is shown that working in the tuple-based format puts the U and L matrix entries into s-expanded form, such as P(s) = ansn+ an-1sn-1+...+ a0, which in turn produces s-expanded transfer functions.

Design of analog integrated circuits is discussed in this paper. The emphasis is on the biasing design of ICs using Fixator-norator pairs. Fixators are used to keep the driver transistors biased at the desirable operating points while the pairing norators are used to allocate and specify the bias-supporting components. A bias-supporting component is shown to be one of the two categories: 1) a DC voltage source or a DC current source/sink or 2) a power-conducting component. A power-conducting component is typically a resistor in lumped circuits but an active load or current mirror in an analog IC. Three types of active loads are introduced and their design is also discussed in this paper. Two examples, one in bipolar and one in CMOS technology, demonstrate the analog IC design procedure.

This letter introduces a new technique for designing and decoding Huffman codes. The key idea is to define a condensed Huffman table (CHT) that is smaller than the ordinary Huffman table and which leads to fast decoding. For example, the new approach has been shown to reduce the memory consumption by a factor of eight, compared with the single-side grown Huffman table.

Code compression is a key element in high-speed digital data transport. A major compression is performed by converting the fixed-length codes to variable-length codes through a (semi-)entropy coding scheme. Huffman coding is shown to be a very efficient coding scheme. To speed up the process of search for a symbol in a Huffman tree and to reduce the memory size we have proposed a tree clustering algorithm to avoid high sparsity of the tree. The method is shown to be extremely efficient in memory requirement, and fast in searching for the symbol. For an experimental video data with Huffman codes extended up to 13 bits in length, the entire memory space is shown to be 122 words, compared to 2/sup 13/=8192 words in a normal situation.>

A new design based on a modified Manchester carry adder is presented. The modification provides bypass routes for the carry to propagate when the carry path through the chain is long. The computational speed received is quite high for high density codes. Much similar to carry look-ahead adders the bypass routes are activated through a series of group carries, in different levels, generated by a NAND/NOR tree network. It is shown that for a 54-bit adder the longest delay through the carry chain is equivalent to the delay through only 11 pass transistors. The algorithm is implemented for the design of a 54-bit adder using CMOS technology.>

An alternative algorithm is presented for multiplication/addition of variable bit-size operands. The algorithm is shown to be fast, and the computational time is variable and dependent on the accuracy requested. The growing nature of the product term, during the course of operation, gives the method some unique computational properties. The algorithm is implemented for the design of 32*32-bit multiplier.>

An algorithm for evaluating the square root of integers and real numbers is developed. The procedure consists of two parts: one to obtain a close estimate of the square root and the other to modify the initial value, iteratively, until a precise root is evaluated. The major effort in this development has been concentrated on two objectives: high speed and no division operation other than division by 2. The first objective is achieved through a simple two-step procedure for getting the first estimate, and then modifying it by employing a fast converging iteration technique. The second objective is also fulfilled through applying bit-shift operation rather than division operation. The algorithm is simulated for both integer and real numbers, and the results are compared to two methods being widely used. The results (tabulated) show considerable improvement in speed compared to these other two methods.>