A new test access mechanism (TAM) for multiple identical embedded cores is proposed. It exploits the identical nature of the cores and modular pipelined circuitry to provide scalable and flexible capabilities to make tradeoffs between test time and diagnosis over the manufacturing maturity cycle from low-yield initial production to high-yield, high-volume production. The test throughput gains of various configurations of this TAM are analyzed. Forward and reverse protocol translations for core patterns applied with this TAM are described.

A new test access mechanism (TAM) for multiple identical embedded cores is proposed. It exploits the identical nature of the cores and modular pipelined circuitry to provide scalable and flexible capabilities to make tradeoffs between test time and diagnosis over the manufacturing maturity cycle from low-yield initial production to high-yield, high-volume production. The test throughput gains of various configurations of this TAM are analyzed. Forward and reverse protocol translations for core patterns applied with this TAM are described.

This paper presents an efficient method to block unknown values for temporal compactors. The control signals for the blocking logic are generated by a linear feedback shift register (LFSR). Control patterns, which describe values required at the control signals of the blocking logic, are compressed by LFSR reseeding. The size of the control LFSR, which is determined by the number of specified bits in the most specified control pattern, is minimized by propagating only one fault effect for each fault and targeting the faults that are uniquely detected by each test pattern. The linear solver to find seeds of the LFSR intelligently chooses a solution such that the impact on test quality is minimal. Very high compression (over 230X) is achieved for benchmark and industrial circuits by the proposed method. Experimental results show that the sizes of control data for the proposed method are smaller than prior work and the runtime of the proposed method is several orders of magnitude smaller than that of prior work. Hardware overhead is very low.

A combined approach for implementing system level test compression and core test scheduling to reduce SoC test costs is proposed in this paper. A broadcast scan based test compression algorithm for parallel testing of cores with multiple scan chains is used to reduce the test data of the SoC. Unlike other test compression schemes, the proposed algorithm doesn't require specialized test generation or fault simulation and is applicable with intellectual property (IP) cores. The core testing schedule with compression enabled is decided using a generalized strip packing algorithm. The hardware architecture to implement the proposed scheme is very simple. By using the combined approach, the total test data volume and test application time of the SoC is reduced to a level comparable with the test data volume and test application time of the largest core in the SoC

In this paper, a novel test point insertion methodology is presented for RTL designs that aim to reduce the data volume of scan-based transition delay tests. Test points are identified based on functional information of RTL primitives using a satisfiability based algorithm. A subset of scan flip-flops is identified for conversion to enhanced-scan, i.e., the values are stored in two flip-flops thereby removing the circuit dependency of the second pattern in broadside transition tests. Using the proposed methodology, the number of specified bits required to test transition faults is reduced thus improving test set compaction. The advantage of test point insertion at RTL is that the extra delay due to multiplexers can be absorbed during logic synthesis. Experimental results show that the proposed methodology can reduce transition test data volume by more than 30% with 1% area overhead and without violating timing constraints.

The entropy of a set of data is a measure of the amount of information contained in it. Entropy calculations for fully specified data have been used to get a theoretical bound on how much that data can be compressed. This paper extends the concept of entropy for incompletely specified test data (i.e., that has unspecified or don't care bits) and explores the use of entropy to show how bounds on the maximum amount of compression for a particular symbol partitioning can be calculated. The impact of different ways of partitioning the test data into symbols on entropy is studied. For a class of partitions that use fixed-length symbols, a greedy algorithm for specifying the don't cares to reduce entropy is described. It is shown to be equivalent to the minimum entropy set cover problem and thus is within an additive constant error with respect to the minimum entropy possible among all ways of specifying the don't cares. A polynomial time algorithm that can be used to approximate the calculation of entropy is described. Different test data compression techniques proposed in the literature are analyzed with respect to the entropy bounds. The limitations and advantages of certain types of test data encoding strategies are studied using entropy theory

This paper presents an efficient method to block unknown values from entering temporal compactors. The control signals for the blocking logic are generated by an LFSR. The proposed technique minimizes the size of the LFSR by propagating only one fault effect for each fault and balancing the number of specified bits in each control pattern. The linear solver to find seeds of the LFSR intelligently chooses a solution such that the impact on test quality is minimal. Experimental results show that sizes of control data for the proposed method are smaller than prior work and run time of the proposed method is several orders of magnitude smaller than that of prior work. Hardware overhead is very low.

The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The ideas proposed in this paper transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing compression while still keeping all the test cubes in the output space. Scan inversion is used to invert a subset of the scan cells while reconfiguration modifies the linear decompressor. Any existing method for designing a linear decompressor (either combinational or sequential) can be used first to obtain the best linear decompressor that it can. Using that linear decompressor as a starting point, the proposed methods improve the compression further. The key property of scan inversion is that it is a linear transformation of the output space and, thus, the output space remains a linear subspace spanned by a Boolean matrix. Using this property, a systematic procedure based on linear algebra is described for selecting the set of inverting scan cells to maximize compression. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for reconfiguring the linear decompressor. The proposed schemes can be utilized in various design flow scenarios and require no or very little hardware overhead. Experiments indicate that significant improvements in compression can be achieved

Increasing test costs has been one of the disadvantageous consequences of technology scaling especially in deep sub-micron designs. The amount of test data required to achieve good test quality has increased tremendously due to the increasing complexity of devices as well as the need to test for newer defect mechanisms that are becoming predominant in smaller device geometries. This has led to the development and deployment of new design-for-test (DFT) technologies to mitigate the problem. Test data compression has been at the forefront of solutions to reduce test costs through reduction in tester storage and test application time. In addition, it has the advantage of needing minimal changes to traditional design flow. The popularity and wide adoption of test data compression can be gauged by the fact that almost all EDA vendors now include test compression with their test solutions. Most test data compression techniques have concentrated on scan test vectors since the bulk of the increase in test data is due to scan vectors, including both stuck-at and delay tests. The test data of scan vectors consist of two parts - the test input or stimulus which is loaded into the scan chains and the test response which is captured at the scan cells after the capture cycle and unloaded through the scan chains for comparison with the correct response. The compression of both these parts present different challenges and hence require separate schemes. The input compression should be loss-less (to avoid reduction in fault coverage) while the response compression is complicated by the presence of unknown values (X's) that are captured in the scan cells. This presentation first briefly summarizes current test data compression techniques. Most of the commercial tools for test data compression utilize on-chip circuits for decompression that belong to the category of linear decompressors. We discuss the limitations of current schemes and look at future challenges. Subsequently, we talk about emerging techniques that seek to overcome these challenges. Several techniques have been developed at NEC Labs for both input test data compression and output (response) compaction. XWRC (Wang et al., 2005) is an externally loaded weighted random pattern compression scheme that combines weighted random pattern testing and LFSR reseeding to achieve very high input compression. PIDISC (Balakrishnan et al., 2006) is a pattern and design independent seed compression scheme to further compress the seeds of LFSR in reseeding based compression schemes. On the output side, a novel compactor to handle test responses with unknown values has been developed (Chao et al., 2005). Response Shaper (2005) is a technique to eliminate the reduction in fault coverage in spatial response compaction due to error masking caused by the appearance of unknown values and even errors. XBlock (Wang et al., 2006) is an efficient LFSR reseeding based technique to block unknown values for temporal compactors

In the past, test data volume reduction techniques have concentrated heavily on scan test data content. However, functional vectors continue to be utilized because they target unique defects and failure modes. Hence, functional vector compression can help alleviate the cost of functional test. Scan vector compression techniques are generally unsuitable in the functional domain and techniques specially tailored for functional test compression are required. Additionally, it may be possible to perform compression and decompression using software techniques without incurring the overhead of dedicated hardware. This paper proposes a set of software techniques targeted towards functional test compression.

A methodology for designing a reconfigurable linear decompressor is presented. A symbolic Gaussian elimination method to solve a constrained Boolean matrix is proposed and utilized for designing the reconfigurable network. The proposed scheme can be implemented in conjunction with any decompressor that has a combinational linear network. Using the given linear decompressor as a starting point, the proposed method improves the compression further. A nice feature of the proposed method is that it can be implemented with very little hardware overhead. Experimental results indicate that significant improvements can be achieved.

This paper presents an input test data compression scheme that combines the advantages of weighted pseudorandom testing techniques and LFSR reseeding. The scheme requires low area overhead and the compression achieved is not limited by the LFSR reseeding bounds. The test data storage requirements of both the static and dynamic versions of the proposed scheme are lower than previously published results. The total numbers of test patterns that need to be applied are much lower than that for any weighted pseudorandom testing or hybrid BIST scheme. Further, the method provides an easy way to trade off between test application time and test data compression. The static version of the scheme can be easily implemented without any modification to the current test generation flow while the dynamic version can be used if the ATPG can be modified. Experimental results on a large industry design show that over 100/spl times/ compression is achievable by the proposed scheme.

The entropy of a set of data is related to the amount of information that it contains and provides a theoretical bound on the amount of compression that can be achieved. While calculating entropy is well understood for fully specified data, this paper explores the use of entropy for incompletely specified test data and shows how theoretical bounds on the maximum amount of test data compression can be calculated. An algorithm for specifying don’t cares to minimize entropy for fixed length symbols is presented, and it is proven to provide the lowest entropy among all ways of specifying the don’t cares. The impact of different ways of partitioning the test data into symbols on entropy is studied. Different test data compression techniques are analyzed with respect to their entropy bounds. Entropy theory is used to show the limitations and advantages of certain types of test data encoding strategies. 1.

The output space of a linear decompressor must be sufficiently large to contain all the test cubes in the test set. The idea proposed in This work is to use scan inversion to transform the output space of a linear decompressor so as to reduce the number of inputs required thereby increasing the encoding efficiency while still keeping all the test cubes in the output space. Any existing method for designing a linear decompressor (either combinational or sequential) can be used first to obtain the best linear decompressor that it can. Using that linear decompressor as a starting point, the proposed method improves the encoding efficiency further. The key property used by the proposed method is that scan inversion is a linear transformation of the output space and thus the output space remains a linear subspace spanned by a Boolean matrix. Using this property, a systematic procedure based on linear algebra is described for selecting the set of inverting scan cells to maximize encoding efficiency. Experiments indicate that significant improvements in encoding efficiency can be achieved.

A new software-based test vector compression technique is proposed for using an embedded processor to test the other components of a system-on-a-chip (SOC). The tester transfers compressed test data to the processor's on-chip memory, and the processor executes a small program which decompresses the data and applies it to the scan chains of each core-under-test. The proposed decompression procedure uses word-based linear operations to expand the compressed test data into the corresponding deterministic test vectors. It has a number of nice features that overcome the drawbacks of software-based linear feedback shift register (LFSR) reseeding. The storage requirements for the proposed approach depend only on the total number of specified bits in the test set. There are no restrictions on static compaction or the test generation procedure as a whole. The decompression program can be easily reused for applying different test sets. Experimental results demonstrate that the proposed approach compares very favorably with all previously published results for software-based test vector decompression.