We present a comprehensive and flexible test scheduling environment, called FITS, for testing core-based system-on-chips. Our environment prevents formation of hot spots during test. It also allows trade-off among test time, test access mechanism, power, and test controller/resource constraints. The basic strategy is to use power profile over application time and structural grids of nonembedded cores to find the best test schedule of their test pattern subsets while satisfying the constraints. As case studies, four integer linear programming formulations, corresponding to four power approximation models, are extensively analyzed. With proper setting of the weights and constraints, optimized results can be obtained quickly for each of the four power approximation models. Extensive experimental results are reported based on ISCAS '89 benchmarks and verify the efficiency and flexibility of the FITS environment.

We present a test scheduling methodology for core-based system-on-chips that can avoid hot spots and allows tradeoff between physical power dissipation and overall test time. A mixed integer linear programming formulation is presented to globally perform the power-time tradeoff, satisfy constraints, and produce the SoC test schedule.

We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use the power profile of nonembedded cores to find the best mix of their test pattern subsets that satisfy the power and/or time constraints. An MILP formulation is presented to globally perform the power-time tradeoff and produce the SoC test schedule. Many constraints including peak/average power of cores, time/sequencing requirements, and ATE pin limitation are also incorporated within this formulation.

Presents a test methodology to allow testing high-speed circuits with low-speed ATEs. The basic strategy is adding an interface circuit to partially supply test data, coordinate sending the test patterns and collecting the signatures. An ILP formulation is presented to globally optimize such coordination in terms of the overall test time and the hardware cost.