Rotation-equivariance is an essential yet challenging property in oriented object detection. While general object detectors naturally leverage robustness to spatial shifts due to the translation-equivariance of the conventional CNNs, achieving rotation-equivariance remains an elusive goal. Current detectors deploy various alignment techniques to derive rotation-invariant features, but still rely on high capacity models and heavy data augmentation with all possible rotations. In this paper, we introduce a Fully Rotation-Equivariant Oriented Object Detector (FRED), whose entire process from the image to the bounding box prediction is strictly equivariant. Specifically, we decouple the invariant task (object classification) and the equivariant task (object localization) to achieve end-to-end equivariance. We represent the bounding box as a set of rotation-equivariant vectors to implement rotation-equivariant localization. Moreover, we utilized these rotation-equivariant vectors as offsets in the deformable convolution, thereby enhancing the existing advantages of spatial adaptation. Leveraging full rotation-equivariance, our FRED demonstrates higher robustness to image-level rotation compared to existing methods. Furthermore, we show that FRED is one step closer to non-axis aligned learning through our experiments. Compared to state-of-the-art methods, our proposed method delivers comparable performance on DOTA-v1.0 and outperforms by 1.5 mAP on DOTA-v1.5, all while significantly reducing the model parameters to 16%.

The hazardous material transportation requires extensive care owing to the disastrous consequences of accidents, such as chemical spills or radioactive exposures. Consequently, a minimum risk delivery plan that is dynamically decided by the cargo load of the vehicle at each customer must be scheduled. We introduce a traveling salesman problem (TSP) with a sequence-and-load dependent risk, which differs from the conventional TSP as the arc costs are determined by the hazardous cargo load at each decision epoch. We define our problem in a dynamic programming formulation and present mixed-integer linear program with a nonlinear objective function. To efficiently retrieve exact optimal solutions, we propose an iterative-deepening A*-based tree search algorithm using admissible lower and efficient upper bound algorithms for guaranteed optimality. Numerical experiments indicate that the proposed algorithm outperforms a current state-of-the-art solver. An ablation study and sensitivity analysis demonstrate the effectiveness of the proposed algorithm and derive managerial insights.

Following considerable development in 3D scanning technologies, many studies have recently been proposed with various approaches for 3D vision tasks, including some methods that utilize 2D convolutional neural networks (CNNs). However, even though 2D CNNs have achieved high performance in many 2D vision tasks, existing works have not effectively applied them onto 3D vision tasks. In particular, segmentation has not been well studied because of the difficulty of dense prediction for each point, which requires rich feature representation. In this paper, we propose a simple and efficient architecture named point projection and back-projection network (PBP-Net), which leverages 2D CNNs for the 3D point cloud segmentation. 3 modules are introduced, each of which projects 3D point cloud onto 2D planes, extracts features using a 2D CNN backbone, and back-projects features onto the original 3D point cloud. To demonstrate effective 3D feature extraction using 2D CNN, we perform various experiments including comparison to recent methods. We analyze the proposed modules through ablation studies and perform experiments on object part segmentation (ShapeNet-Part dataset) and indoor scene semantic segmentation (S3DIS dataset). The experimental results show that proposed PBP-Net achieves comparable performance to existing state-of-the-art methods.

An effective lane-detection algorithm is a fundamental component of an advanced driver assistant system, as it provides important information that supports driving safety. The challenges faced by the lane detection and tracking algorithm include the lack of clarity of lane markings, poor visibility due to bad weather, illumination and light reflection, shadows, and dense road-based instructions. In this paper, a robust and real-time vision-based lane detection algorithm with an efficient region of interest is proposed to reduce the high noise level and the calculation time. The proposed algorithm also processes a gradient cue and a color cue together and a line clustering with scan-line tests to verify the characteristics of the lane markings. It removes any false lane markings and tracks the real lane markings using the accumulated statistical data. The experiment results show that the proposed algorithm gives accurate results and fulfills the real-time operation requirement on embedded systems with low computing power.

As the integration scale of a chip increases, on-chip interconnects suffer from the increased area occupied by a large number of bus signals. To reduce the overhead for communication, this paper formulates a new concept of an on-chip communication approach, called phase-based interconnection, with an example protocol, system-on-chip network protocol (SNP). In the phase-based communication, a small number of signals called phase signals are used to distinguish the types of signals transmitted through the main communication channel. To identify transactions transmitted through the channel, the SNP protocol defines the allowed sequence of phases for each transaction. A theoretical framework provides conditions for a phase-based protocol to allow immediate decoding of transactions. Simulation results show that the bandwidth of SNP is greater than that of a de facto standard bus protocol although SNP has wires only about three-fifths of the standard bus protocol. Although the signal-toggling rate is increased because of the multiplexed transmission of various signals through a single communication channel, simulation results show that the increase is not significant for multimedia applications that frequently transmit burst transfers. The phase omission of SNP helps to reduce the transaction failure rate to 65% while the hardware implementation cost for the support of phase omission is negligible.

This paper presents the design and implementation of the InfiniBand link layer with special efforts made for packet latency reduction and buffer space optimization. The link layer is designed to avoid any architectural conflict while its components are executed in parallel as far as possible. For high-speed packet processing with the various quality of service supports required by InfiniBand, three candidates for packet receiving architecture are investigated. The maximum and minimum delays from an input to an output of a switch adopting each of the three candidates is estimated by mathematically modeling the switch delays. Then, the candidate architecture with the best performance is chosen, and a novel first-in first-out (FIFO) is designed to efficiently implement the chosen architecture. Simulation results show that the chosen architecture achieves the least packet latency and uses the least memory space among the three candidates. The link layer core is implemented in an InfiniBand host channel adapter system-on-chip called KINCA.

The reusability of an IP can be increased when it is developed according to a standard bus interface. Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. We have proposed SNA (SoC network architecture) which is high performance on-chip-bus architecture with SNP (SoC network protocol), to solve the problems of the conventional shared bus. Now, we refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting multiple routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs an extended SNP that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. It guarantees simultaneous multiple channels. Thanks to the small number of interconnection wires, the SNA can also be used for the off-chip bus system

This paper proposes and investigates a short-channel MOSFET model down to a 0.1-/spl mu/m regime for the frequency-domain analysis of the device operation through the harmonic balance technique. The efficiency and the preciseness of our method are validated by comparison of simulation results with the two-dimensional time-domain simulation tool, MEDICI. Along with the carrier transport model, the displacement current components are included in the terminal current equations for the extended analysis under external circuit environments.