Continuing a tradition at the IEEE VLSI Test Symposium this new topic session presents two interesting talks on new emerging computing and testing techniques. The first talk focuses on carbon nanotube electronics while the second talk discusses about wafer level testing under magnetic field.

In recent years, a clear path towards larger-scale quantum processors has emerged to study and eventually exploit the power of quantum computers at scale. The rapid progress has been observed in quantum computers, semiconductor implementations, and new generation of application development. The speakers will provide a perspective on the numerous challenges and their perspective on the future.

Power electronics covers various disciplines, especially semiconductor, circuit design, thermal design (heat transfer, fluid flow), electromagnetics (EMI, Inductors, transformers), digital electronics, control theory, and materials science in the context of packaging and reliability engineering. It also covers a wide range of power (mW to MW), temperature (−55C to 275C), frequencies (DC to GHz) and dimensions (um to km). The global power electronics market is worth over $200Bn and is seeing significant growth in sectors such as aerospace, automotive and energy generation, transmission and distribution. This presentation will discuss the current status and future challenges in the design of power electronics components and systems. In particular co-design in terms of the modeling and analysis toolsets that enable power electronics designers to undertake thermal, electromagnetic and mechanical analysis of new power electronics components and systems, as well as the need for an holistic approach to designing such systems from the devices to convertors and drives in an integrated manner.

MEMS sensors are driving the internet of things and the market for MEMS is growing rapidly. In many MEMS products, test strategies are not standardized, proprietary, and considered important intellectual property. However, an eco-system is beginning to form as equipment makers are developing dedicated MEMS test equipment and test houses offer services for testing MEMS. This talk describes the challenges and opportunities for MEMS testing. Current MEMS testing is compared to the established methods of VLSI test. The talk further describes how design for test concepts can be applied to MEMS design. Finally, testing MEMS integrated within larger systems is highlighted.

In this talk, a unitary perspective is given on the design challenges involved in ultra-low voltage (ULV) VLSI circuits and systems, as well as on directions to tackle them. Innovative approaches are described to improve the energy efficiency of ULV systems, while maintaining adequate resiliency and yield with low overhead. Experimental results based on the testing of 65-nm to 28-nm prototypes are presented to develop a quantitative sense of the achievable benefits. Emphasis is given on applications that require extremely high energy efficiency, such as compact portable devices and energy-autonomous VLSI systems. Although CMOS is the mainstream choice for the foreseeable future, Tunnel FETs (TFETs) are introduced as very promising alternative that favors more aggressive voltage scaling and energy reduction. Although still immature, device-circuit co-design is shown to be critical to the success of such technology. Potential of TFETs is discussed in a general framework through representative metrics and vehicle circuits, emphasizing how design will be impacted by their adoption.

Consider a re-spin of an existing complex SoC, with a partial schematic and an incomplete specification, with limited abilities to test and observe I/O behavior. Additionally, the underlying technology used is only partially understood. Can disciplined engineering approaches yield the re-spin? What are fundamental challenges? How will automation tools enable such designs? This talk will showcase how analysis and synthesis concepts can be applied in the context of biological discovery and design. Various optimization and analysis techniques can be applied to maximize the production of ethanol within an E. Coli cell without kill it. Pathway synthesis techniques can help uncover the fate of environmental chemicals within the human gut, which is colonized by ∼1014 bacteria belonging to ∼1000 species. No biology pre-requisites are needed to attend this talk.

Summary form only given, as follows. The complete presentation was not made available for publication as part of the conference proceedings. Process variations complicate at-speed testing enormously. Different paths have different sensitivity signatures, and therefore each chip can potentially have a different critical path depending on the manufacturing parameters of that chip. This presentation will discuss how process variations can systematically be covered by exploiting statistical timing to select paths for at-speed structural test. Simultaneous coverage of process variations and satisfaction of sensitization conditions will be discussed. Due to increasing process variability in modern technologies, selection of optimal test margins is important to reduce pessimism while ensuring quality of shipped chips. Use of binning techniques to increase yield in the face of wide process variations is becoming more prevalent. Timing closure, margining and testing for binned chips can also take advantage of statistical timing to improve yield and quality.

This paper discusses several forms of heterogeneity in systems on chip and systems in package. A means to distinguish the various forms of heterogeneity is given, with an estimation of the maturity of design and modeling techniques with respect to various physical domains. Industry-level MEMS integration, and more prospective microfluidic biochip systems are considered at both technological and EDA levels. Finally, specific flows for signal abstraction heterogeneity in RF SiP and for functional co-verification are discussed

According to the Moore’s Law, the number of transistors per integrated circuit doubles every 24 months, and it has been the guiding principle for the silicon semiconductor industry for over 30 years. The sustaining of the Moore’s Law, however, requires continued transistor scaling and performance improvement.

A major problem for applying self-test techniques to MEMS is the multi-domain nature of the sensing parts that require special test equipment for stimuli generation. In this work we describe, for three different types of MEMS that work in different energy domains, how the required nonelectrical test stimuli can be induced onchip by means of electrical signals. This provides the basis for adding BIST strategies for MEMS parts embedded in the coming generation of integrated systems. The first case corresponds to an accelerometer as a review of a classical example. The last two cases correspond to piezoresistive and infrared sensors that we use in innovative applications under development in our Laboratory, and for which the self-test methods are new to our knowledge. The last case is also illustrated as a complete application that corresponds to an infrared imager. The on-chip test signal generation proposed requires only slight modifications and allows production test of the imager with a standard test equipment, without the need of special infrared sources and the associated optical equipment. The test function can also be activated off-line in the field for validation and maintenance purposes.

This paper illustrates an approach to design and validation of heterogeneous systems. The emphasis is placed on devices which incorporate MEMS parts in either a single mixed-technology (CMOS + micromachining) SOC device, or alternatively as a hybrid system with the MEMS part in a separate chip. The design flow is general, and it is illustrated for the case of applications embedding CMOS sensors. In particular, applications based on finger-print recognition are considered since a rich variety of sensors and data processing algorithms can be considered. A high level multi-language/multi-engine approach is used for system specification and co-simulation. This also allows for an initial high-level architecture exploration, according to performance and cost requirements imposed by the target application. Thermal simulation of the overall device, including packaging, is also considered since this can have a significant impact in sensor performance. From the selected system specification, the actual architecture is finally generated via a multi-language co-design approach which can result in both hardware and software parts. The hardware parts are composed of available IP cores. For the case of a single chip implementation, the most important issue of embedded-core-based testing is briefly considered, and current techniques are adapted for testing the embedded cores in the SOC devices discussed.

A design methodology for on-line testing analog linear fully differential (FD) circuits is presented in this work. The test strategy is based on concurrently monitoring via an analog checker the common mode (Chi) at the inputs of all amplifiers, The totally self-checking (TSC) goal is achieved for linear FD implementations provided that the checker CM threshold is small enough with respect to the specified margins of erroneous behavior in the circuit outputs. The design methodology is illustrated for a switched-capacitor biquadratic filter and the self-checking properties evaluated for a hard/soft-fault model. A large checker threshold of 100 mV of CM is chosen since the filter implementation does not minimize nonidealities (e.g., amplifier offsets or clock feedthrough) which result in significant CM components. The circuit outputs are accepted to deviate within a 10% band. With the implemented checker, the TSC goal is not achieved for some faults in narrow regions of the frequency band. For the worst case, a hard fault which results in a 31% deviation is undetected in only a narrow band of approximately 310 Hz. The circuit can be made TSC with a checker threshold of 40 mV and an accepted output deviation of 15%. This is, however, more demanding on the checker (which currently takes less than 3% of the total area and about 7.6% of the total power) and requires an improved filter implementation to reduce CM components. Our solution consists of relaxing a bit the TSC property of the functional block and applying a periodical off-line test to make the checker strongly code disjoint (SCD). This is easy to implement since an off-line test is also required for the checker. The checker outputs a double-rail error indication which ensures compatibility with digital checkers and makes the design of self-checking mixed signal circuits straightforward. The circuit-level mixed-signal approach is extended to the board level by means of the IEEE Std. 1149.1 digital test bus.

As next generation chips embedding MEMS appear, fault-based and defect-oriented tests for MEMS parts become important for cost-effective production testing. This paper presents realistic fault modeling and simulation techniques for suspended thermal MEMS, an already successful domain of application.

In this work a Computer-Aided Testing (CAT) tool is proposed that brings a systematic way of dealing with testing problems in emerging microsystems. Experiments with case-studies illustrate the techniques and tools embedded in the CAT environment. Some of the open problems that shall be addressed in the near future as an extension to this work are also discussed.

This paper addresses three topics: First, a new three-dimensional CMOS-SOI on SOI technology is presented, then design methodologies are proposed for this technology and last, a comparison is carried out between 2D and 3D designs. In this technology the P-channel devices are stacked over the N-channel ones. All gates are l00nm length. New design constraints are introduced. Consequently, new design methodologies have to be developed in order to fully take advantage of the outstanding features of 3D integration like for example the reduced length of interconnections. A 16×l6 bit multiplier was designed in this technology. Comparative results between 2D and 3D integration are given here in terms of energy consumption, delay and area

Silicon-compatible micromachining provides a low cost monolithic solution for the integration of microelectromechanical systems (MEMS). In the last years, CMP (the French MultiProject Wafer Service) has made available technological solutions for the fabrication of CMOS-compatible MEMS. Numerous monolithic devices have been fabricated using this service. The inspection of failed devices has allowed the identification of the most typical failure mechanisms and design errors for this type of MEMS. This valuable information, together with a detailed analysis of the fabrication processes, is used in this paper to provide a classification of faults in silicon-compatible MEMS which can later be used for fault simulation and testing.

The paper describes a fault tolerant system that is based on two replicas of a self checking module and on an error masking interface. The main contributions of this work rely on the fail safe/strongly fail safe design of the error masking interface, and on the analysis of the competitiveness of this fault tolerant scheme with respect to its reliability.

Besides foundry facilities, Computer-Aided Design (CAD) tools are also required to move microsystems from research prototypes to an industrial market. Currently available CAD tools need extensions before they can be used for the automated design of micromachined devices. This paper presents a low cost access to microsystem technology (MST), applied by the CMP service, and based on the use of existing microelectronics production lines, with additional post-processing for microsystem specific 2D and 3D structures, and a global CAD approach for the design and simulation of microsystems applied to currently available commercial CAD tools, e.g. Mentor Framework, in order t o ensure a continuous flow from the design to the manufacturing.

The continuously increasing power densities in integrated circuits necessitated the introduction of DfTT (Design for Thermal Testability) design methodology to prevent overheating effects. Newly developed CMOS temperature sensors enable the application of DfTT principle in safety-critical circuits. Parameters and operation principles of the low-power small-area temperature sensor family are presented in details in the paper, followed by the discussion of placement and testing strategies.

On-line temperature monitoring of safety-critical ICs and systems becomes more and more crucial because of downsizing of integrated circuits and of increased density due to advanced packaging. To prevent erroneous operation, temperature sensors should be placed on the critical spots, the outputs of which should be read by means of boundary scanned architectures or modified boundary scanned architectures in case of on-line monitoring.

In this paper we propose a configuration for a VLSI analog sine wave generator with an appropriate frequency BIST. The generator is used for testing circuits that require sinusoidal input signals with a variable frequency as an input stimulus. The detectors indicate any deviation of the frequency input signal from the nominal value /spl plusmn//spl epsiv/. A sine wave generator and two different BISTs are proposed: the defection and translation (DandT) T-BIST approach and the frequency-counter BIST approach. Some experimental results are also presented.

We propose a new scheme for built-in test (BIT) that uses multiple-polynomial linear feedback shift registers (MP-LFSR's). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear equations involving the seed variables for the positions where the test cubes have specified values. We demonstrate that MP-LFSR's produce sequences with significantly reduced probability of linear dependence compared to single polynomial LFSR's. We present a general method to determine the probability of encoding as a function of the number of specified bits in the test cube, the length of the LFSR and the number of polynomials. Theoretical analysis and experiments show that the probability of encoding a test cube with s specified bits in an s-stage LFSR with 16 polynomials is 1-10/sup -6/. We then present the new BIT scheme that allows for an efficient encoding of the entire test set. Here the seeds are grouped according to the polynomial they use and an implicit polynomial identification reduces the number of extra bits per seed to one bit. The paper also shows methods of processing the entire test set consisting of test cubes with varied number of specified bits. Experimental results show the tradeoffs between test data storage and test application time while maintaining complete fault coverage.>

The design of checkers aimed at the concurrent test of analog and mixed-signal circuits is considered in this paper. These checkers can on-line test duplicated and fully differential analog circuits. The test approach is based on exploiting the inherent redundancy of these circuits which results in the use of a code for the analog signals. The analog code is monitored by the checkers. An error signal which complies with existing digital self-checking parts is generated in the case that a code fails out of the valid code space. For the verification of the analog codes, absolute tolerance margins and tolerance margins which are made relative to signal amplitude are considered. A test pattern generator for off-line testing of the checkers is proposed.>

An approach to the test and diagnosis of fully dif-ferential analogue circuits is described in this paper. The test approach is based on o-line monitoring via an analogue BIST observer the inputs of the opera-tional ampliers in the circuit. The analogue BIST can detect both hard and soft faults. Diagnosis resolu-tion is improved by also monitoring the outputs of the operational ampliers. Faulty components can then be located and the actual defective value of a faulty pas-sive component determined. 1

The design of checkers suitable for concurrent error detection in analogue and mixed-signal circuits is addressed in this paper. These checkers can on-line test duplicated and fully differential analogue functional circuits and comply with existing digital self-checking parts. A test pattern generator for off-line testing of the checkers is proposed, which fully exercises their capability of signalling functional error occurrences.>

This paper presents a study of the behavior of a built-in current sensor (BICS) to be used for online concurrent error detection in circuits working in radiation-exposed environments. BIC sensors are used to monitor the power-bus static current of these circuits to detect excessive current consumption. This excessive static current consumption is compared to a predefined reference value in order to detect radiation-induced multiple parametric failures and system power supply breakdown. BIC sensors can also be affected by these faults and the reliability of the system can be lost. However, we show that the proposed current sensor is strongly code disjoint (SCD) with respect to the above faults and the system reliability is guaranteed.>

In this paper the Boundary Scan technique and the Un@ed Built-In Self-Test scheme are combined in order to propose a strategy suitable for the manufacturing, the field testing and the concurrent error detection on integrated circuits and board interconnects. Such unification of the off-line and the on-line testing plays a major role in the design for broad testability of self-checking boards. This unified test strategy is primarily aimed at critical application designs: transportation systems, nuclear plants, etc.. ., which are the main targets. This architecture, oriented primarily towards the off-line test, provides efficient means of testing of circuits and board interconnects. The association of BIST and BS techniques leads to a significant reduction of the automatic test equipment complexity, due to lower memory requirements and weaker test time constraints. The other part of the tests necessary for circuits and boards is related to the on-line testing capability, a feature of great importance for systems where poor functioning can, for example, lead to a disaster. This is the case of railway, automotive and nuclear systems, where errors must be detected before they contaminate other units and at a point where basic repair is still possible. The self-checking circuit implementation, for making on-line testing possible, is based on the encoding of functional block outputs and on the verification of

The authors present a novel approach to the test of multi-port RAMs. A novel fault model that takes into account complex couplings resulting from simultaneous access of memory cells is used in order to ensure a very high fault coverage. A novel algorithm for the test of dual-port memories is detailed. This algorithm achieves O(n) complexity thanks to the use of some topological restrictions. The authors also present a novel built-in self-test (BIST) scheme, based on programmable schematic generators, that allows great flexibility for ASIC (application-specific integrated circuit) design.>

The authors deal with prototype validation of VLSI circuits. Circuits are observed using electron-beam probing used in voltage contrast mode, in such a way that gray-level images are obtained and processed in order to determine potential values of connexions. These values are compared against reference values, issued from fault-free simulation of the device under test. The list of discrepancies resulting from comparison constitutes input for a fault localization process done using a knowledge-based system. The reasons for the choice for such an approach are explained, and the approach itself is described, as well as its implementation and the obtained results.

The number of (random) patterns required for random testing of RAMs (random-access memories), when classical fault models including pattern-sensitive faults are considered is determined. Markov chains are a powerful tool for this purpose. Single faults are considered first, and the influence of different parameters is analyzed. Double faults are then considered and arguments are presented to extend the results to all multiple-coupling faults. Those results are compared to the optimal or best-known number of test patterns required when deterministic testing is considered, for the same fault models.>

The authors describe a design-for-testability strategy for the SYCO control section compiler (CPC). The SYCO CPC translates high-level descriptions into mask-level specification for hierarchical control sections, which are composed of a stack of control section slices, each one organized around a programmable logic array. The proposed design-for-testability scheme is called UBIST (unified built-in self-test) and ensures a high quality for all tests needed for integrated circuits (i.e. online and offline tests). The authors elucidate the concept of UBIST and show how to modify SYCO CPC data structure and its automatic layout synthesizer to generate UBIST control sections automatically and efficiently.>

A fault simulation and test-pattern-generation environment is specified. It includes a multiple-valued algebra, allows the natural treatment of loops and bidirectional devices, and models the physical failures. The authors' main idea is to define what is possible when no extraction to gate level and no creation of transistor groups are performed. Two fault groups are distinguished: the faults which can be modelled in a downward layout, and the faults which can be modelled in an upward verification. This distinction induces difference in the switch network obtained, as the second group allows to model the line resistances.>

Strongly language-disjoint (SLD) checkers are to sequential systems what strongly code-disjoint checkers are to combinatorial systems. SLD checkers are the largest class of checkers with which a functional system can achieve the totally self-checking goal. Self-checking sequential systems are first addressed, and formal definitions of SLD checkers are given. The design of SLD checkers based on regular combinatorial self-checking components is then considered.>

Strongly code-disjoint (SCD) checkers are defined and shown to include totally self-checking (TSC) code-disjoint checkers. This type of checker is the natural companion of strongly fault-secure (SFS) networks. SCD checkers are the largest class of checkers with which a combinational system may achieve the TSC goal. Some examples are given to illustrate the design of SCD checkers.>

The SYCO system is a silicon compiler for VLSI circuits specified by algorithms. The SYCO system starts from an algorithmic description and produces a microprocessor-like circuit that realizes the algorithm. It uses a target architecture based on a multiple interpretation level scheme. A large interpreter of a given command language is split into a set of interpreter levels. Each interpreter level breaks down the commands given by the upper level into a set of sub-commands for the lower level. Each interpreter level is implemented by a block of layout called a layout slice. A chip will contain one data path slice and several control section slices. The SYCO system makes use of a set of specialized compilers to produce the layout of the datapath and of the control section slices. These slices are generated to be automatically assembled together. The whole system is written in Le Lisp. It is expected that the SYCO system will give the ability to compile circuits, which have the complexity of the MC68000. The SYCO system is developed in the framework of the SYCOMORE French National Project for CAD of VLSI.