We study the notion of k-stabilizer universal quantum state, that is, an n-qubit quantum state, such that it is possible to induce any stabilizer state on any k qubits, by using only local operations and classical communications. These states generalize the notion of k-pairable states introduced by Bravyi et al., and can be studied from a combinatorial perspective using graph states and k-vertex-minor universal graphs. First, we demonstrate the existence of k-stabilizer universal graph states that are optimal in size with n = Θ(k²) qubits. We also provide parameters for which a random graph state on Θ(k²) qubits is k-stabilizer universal with high probability. Our second contribution consists of two explicit constructions of k-stabilizer universal graph states on n = O(k⁴) qubits. Both rely upon the incidence graph of the projective plane over a finite field 𝔽_q. This provides a major improvement over the previously known explicit construction of k-pairable graph states with n = O(2^{3k}), bringing forth a new and potentially powerful family of multipartite quantum resources.

We propose a post-processing method for message-passing (MP) decoding of CSS quantum LDPC codes, called stabilizer-inactivation (SI). It relies on inactivating a set of qubits, supporting a check in the dual code, and then running the MP decoding again. This allows MP decoding to converge outside the inactivated set of qubits, while the error on these is determined by solving a small, constant size, linear system. Compared to the state of the art post-processing method based on ordered statistics decoding (OSD), we show through numerical simulations that MP-SI outperforms MP-OSD for different quantum LDPC code constructions, different MP decoding algorithms, and different MP scheduling strategies, while having a significantly reduced complexity.

This paper investigates decoder diversity architectures for short low-density parity-check (LDPC) codes, based on recurrent neural network (RNN) models of the belief-propagation (BP) algorithm. We propose a new approach to achieve decoder diversity in the waterfall region, by specializing BP-RNN decoders to specific classes of errors, with absorbing set support. We further combine our approach with an ordered statistics decoding (OSD) post-processing step, which effectively leverages the bit-error rate optimization deriving from the use of the binary cross-entropy loss function. We show that a single specialized BP-RNN decoder combines better than BP with the OSD post-processing step. Moreover, combining OSD post-processing with the diversity brought by the use of multiple BP-RNN decoders, provides an efficient way to bridge the gap to maximum likelihood decoding.

The significant amount of unused spectrum in sub-TeraHertz frequencies is contemplated to realize high rate wireless communications for beyond 5G networks. Yet, the performance of radio-frequency sub-TeraHertz systems is severely degraded by strong oscillator phase noise. Therefore, we investigate in this paper the use of multiple-input multiple-output (MIMO) systems with energy detection receivers to achieve high rate communications robust to phase noise. First, the design of the receiver detection algorithm is addressed. Two detectors are proposed for the studied nonlinear MIMO channel, either derived from the maximum likelihood decision rule by using a Gaussian approximation, or based on the use of neural networks. Second, the communication performance is assessed through numerical simulations for uncoded and coded systems. We consider a realistic scenario modeling an indoor wireless link in D-band with directive antennas and strongly correlated line-of-sight channels. Our results demonstrate that spatial multiplexing with non-coherent sub-TeraHertz transceivers can be realized on strongly correlated line-of-sight channels using the proposed detection schemes. Thereby, we highlight that high-rate radio-frequency sub-TeraHertz systems can be implemented with low-complexity and low-power architectures using MIMO systems with energy detection receivers.

We provide a generalization of quantum polar codes to quantum channels with qudit-input, achieving the symmetric coherent information of the channel. Our scheme relies on a channel combining and splitting construction, where a two-qudit unitary randomly chosen from a unitary 2-design is used to combine two instances of a qudit-input channel. The inputs to the synthesized bad channels are frozen by sharing EPR pairs between the sender and the receiver, so our scheme is entanglement assisted. Using the fact that the generalized two-qudit Clifford group forms a unitary 2-design, we conclude that the channel combining operation can be chosen from this set. Moreover, we show that polarization also happens for a much smaller subset of two-qudit Cliffords, which is not a unitary 2-design. Finally, we show how to decode the proposed quantum polar codes on Pauli qudit channels.

36 pages, 7 figures, second version extending [v1] Submitted to IEEE Transactions on Informations Theory

We propose a decoding algorithm for color codes over the quantum erasure channel, which is linear-time maximum likelihood (ML) when the set of erased qubits satisfies a certain condition called trimmability. Two methods are proposed for general erasure sets, either by extending the erasure set to make it trimmable, or by inactivating some vertices. The former is linear time but not ML, while the latter is ML but not linear time. Numerical results are provided to assess the error correction performance and the complexity of both methods.

The significant amount of unused spectrum in sub-TeraHertz frequencies is contemplated to realize high rate wireless communications for beyond 5G networks. Yet, the performance of sub-TeraHertz systems is severely degraded by strong oscillator phase noise. Therefore, we investigate in this paper the use of multiple-input multiple-output (MIMO) systems with energy detection receivers to achieve high rate communications robust to phase noise. First, the design of the receiver detection algorithm is addressed. We derive the joint maximum likelihood detector corresponding to the studied nonlinear MIMO channel. Second, the system performance is assessed through numerical simulations. We consider a realistic scenario modeling an indoor wireless link with directive antennas and strongly correlated line-of-sight channels. Our results demonstrate that high rate sub-TeraHertz systems can be implemented on low-complexity and low-power architectures using MIMO systems and energy detection receivers.

We provide a purely quantum version of polar codes, achieving the coherent information of any quantum channel. Our scheme relies on a recursive channel combining and splitting construction, where random two-qubit Clifford gates are used to combine two single-qubit channels. The inputs to the synthesized bad channels are frozen by sharing EPR pairs between the sender and the receiver, so our scheme is entanglement assisted. We further show that a Pauli channel polarizes if and only if a specific classical channel over a four-symbol input set polarizes. We exploit this equivalence to prove fast polarization for Pauli channels, and to devise an efficient successive cancellation based decoding algorithm for such channels.

The Probabilistic Gradient Descent Bit-Flipping (PGDBF) decoder offers a significant improvement in decoding performance for Low-Density Parity-Check (LDPC) codes on Binary Symmetric Channel (BSC). However, this outstanding decoding performance comes along with a non-negligible extra hardware cost to realize the probabilistic behavior on top of the deterministic Gradient Descent Bit-Flipping (GDBF) decoder. This paper presents a novel solution to implement PGDBF decoder on Quasi-Cyclic LDPC codes. The proposed architecture takes advantage of the cyclic shift permutation nature of QC-LDPC and changes the message flow such that a probabilistic behavior is emulated without the cost of an actual probabilistic signal generator. It is shown that, the proposed architecture improves the PGDBF decoding performance with respect to the state-of-the-art implementation while reducing hardware complexity, even being lower than that of the deterministic GDBF. The efficiency of our proposed method is verified through the ASIC 90nm CMOS technology implementations and decoding simulations.

This paper proposes a generalization of the recently introduced successive cancellation flip (SCFlip) decoding of polar codes, characterized by a number of extra decoding attempts, where one or several positions are flipped from the standard SC decoding. To make such an approach effective, we first introduce the concept of higher order bit flips and propose a new metric to determine the bit flips that are more likely to correct the trajectory of the SC decoding. We then propose a generalized SCFlip decoding algorithm, referred to as dynamic-SCFlip (D-SCFlip), which dynamically builds a list of candidate bit flips, while guaranteeing that the next attempt has the highest probability of success among the remaining ones. Simulation results show that D-SCFlip is an effective alternative to SC-list decoding of polar codes, by providing very good error correcting performance, with an average computation complexity close to the one of the SC decoder.

This paper introduces a new approach to cost-effective, high-throughput hardware designs for low-density parity-check (LDPC) decoders. The proposed approach, called nonsurjective finite alphabet iterative decoders (NS-FAIDs), exploits the robustness of message-passing LDPC decoders to inaccuracies in the calculation of exchanged messages, and it is shown to provide a unified framework for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for regular and irregular LDPC codes, and are shown to provide different tradeoffs between hardware complexity and decoding performance. Two hardware architectures targeting high-throughput applications are also proposed, integrating both Min-Sum (MS) and NS-FAID decoding kernels. ASIC post synthesis implementation results on 65-nm CMOS technology show that NS-FAIDs yield significant improvements in the throughput to area ratio, by up to 58.75% with respect to the MS decoder, with even better or only slightly degraded error correction performance.

In this paper we introduce a novel error resilient memory architecture potentially applicable to a large range of memory technologies. In contrast with state of the art memory error correction schemes, which rely on (extended Hamming) Error Correcting Codes (ECC), we make use of Low Density Parity Check (LDPC) codes due to their close to the Shannon performance limit error correction capabilities. To allow for a cost-effective implementation we build our approach on top of a 3D memory organization which inherently fast and customizable wide-I/O vertical access allows for a smooth transfer of the required LDPC long code-words to/from an error correction dedicated die. To make the error correction process transparent to the memory users, e.g., processing cores, we propose an online memory scrubbing policy that performs the LDPC-based error detection and correction decoupled from the normal memory operation. For evaluation purposes we consider 3D memories protected by the proposed LDPC mechanism with various data width codes implementations. Simulation results indicate that our proposal clearly outperforms state of the art ECC schemes with fault tolerance improvements by a 4710× factor being obtained when compared to extended Hamming ECC. Furthermore, we evaluate instances of the proposed memory concept equipped with different LDPC codecs implemented on a commercial 40nm low-power CMOS technology and evaluate them on actual memory traces in terms of error correction capability, area, latency, and energy. Our results indicate that the LDPC protected memories offer substantially improved error correction capabilities, when compared to state of the art extended Hamming ECC, being able to assure clean runs for memory error rates α

We consider the joint detection and decoding of m-sequences. The receiver has to decide whether an m-sequence is received and possibly to decode its initial state. To do so, it implements an iterative message-passing decoding algorithm that operates on a parity check matrix, built upon a number of reference parity-check equations satisfied by the m-sequence. This matrix concatenates several elementary parity check matrices which are derived from reference equations. Unlike the conventional decoding case, the detection problem imposes to consider false alarms that may occur when the decoder is only fed with noise. While absorbing sets are known to be responsible for the error floor phenomenon of iterative message-passing decoders, we show that they may have a beneficial effect on the detection performance, in that they may prevent the decoder to produce false alarms. We further compute the number of hybrid cycles of length six and eight in the Tanner graph of the decoder and use the minimization of this number as criterion to derive an algorithm for selecting the reference parity check equations. This algorithm was found to be efficient for minimizing the probability of false alarm and decreases also the probability of wrong detection in the very small SNR region. This has been achieved at the cost of a reduction of the probability of correct detection.

In this paper, we propose a layered LDPC decoder architecture targeting flexibility, high-throughput, low cost, and efficient use of the hardware resources. The proposed architecture provides full design time flexibility, i.e., it can accommodate any Quasi-Cyclic (QC) LDPC code, and also allows redefining a number of parameters of the QC-LDPC code at the run time. The main novelty of the paper consists of: (1) a new low-cost processing unit that merges the logical functionalities of the Variable-Node Unit (VNU) and the A Posteriori Log-Likelihood Ratio (AP-LLR) unit in an efficient way, (2) a high speed, low-cost Check-Node Unit (CNU) architecture, which is executed twice at each iteration in order to complete the computation of the check-node messages, (3) a splitting of the iteration processing in two perfectly symmetric stages, executed in two consecutive clock cycles, each one using exactly the same processing resources, the processing load is perfectly balanced between the two clock cycles, thus yielding an optimal clock frequency. Synthesis results targeting a 65nm CMOS technology for a (3,6)-regular (648,1296) Quasi-Cyclic LDPC code and for the WiMax (1152,2304) irregular QC-LDPC code show significant improvements in terms of area and throughput compared to the baseline architecture discussed in this paper, as well as several state of the art implementations.

A novel fault tolerant methodology known as Codeword Prediction Encoder (CPE) for reliable data transmission using unreliable hardware is proposed. Simulation results show that performance of CPE is much better as compared to transmitting data by employing traditional encoding methodology. It is shown that by employing Min-sum decoding mechanisms and a strong encoder r = 1/2 and dv = 4, it is possible to correct all errors given that gate errors smaller than Pg = 6e-4. In general, CPE performance improvement of upto 10K is observed when compared to the normal encoding mechanism.

This paper focuses on the recently introduced Successive Cancellation Flip (SCFlip) decoder of polar codes. Our contribution is twofold. First, we propose the use of an optimized metric to determine the flipping positions within the SCFlip decoder, which improves its ability to find the first error that occurred during the initial SC decoding attempt. We also show that the proposed metric allows closely approaching the performance of an ideal SCFlip decoder. Second, we introduce a generalisation of the SCFlip decoder to a number of ω nested flips, denoted by SCFlip-ω, using a similar optimized metric to determine the positions of the nested flips. We show that the SCFlip-2 decoder yields significant gains in terms of decoding performance and competes with the performance of the CRC-aided SC-List decoder with list size L=4, while having an average decoding complexity similar to that of the standard SC decoding, at medium to high signal to noise ratio.

In this paper, we investigate optimal control of cell discontinuous transmission (DTX) for small cells in heterogeneous cellular networks (HetNets). The small cell transmission activity is dynamically orchestrated in a centralized way to jointly minimize the power consumption of Radio Access Network (RAN) and backhaul (BH), while at the same time satisfying user Quality of Service (QoS) constraints. We propose a Fuzzy Q-Learning scheme that combines Reinforcement Learning (RL) and Fuzzy Inference System (FIS) theory to enable system optimization in realistic environments. Our analysis shows that 1) joint RAN and BH optimization is necessary to correctly design network energy saving functions and 2) the proposed controller results in notable energy saving with respect to the classic DTX approach.

LDPC decoders on faulty hardware have received increasing attention over the last few years, mainly motivated by reliability issues in emerging nanotechnologies. As a main result, it was shown that LDPC decoders are naturally robust to hardware faults. LDPC encoders on faulty hardware have received less attention, and they are expected to be less robust to hardware faults. In this work, we propose an LDPC encoding solution that is robust to faulty hardware. Our encoding solution is composed of two steps. First, an Augmented Encoding method is proposed, which consists in computing an augmented codeword that contains both the codeword to be transmitted on the channel and extra parity bits. The augmented codeword is computed from a noisy encoding circuit, and then corrected by a noisy Gallager-B decoder before channel transmission. The augmented codeword is obtained from a rate-compatible construction that guarantees good decoding performance both for the augmented codeword and for the codeword to be transmitted on the channel. In order to further improve the robustness of our encoding solution, we propose a second step, consisting of a circuit-level optimization. We propose to identify the critical gates that are responsible for encoding failures, and to duplicate them in order to reduce their influence on encoding outputs. Based on Monte-Carlo simulation, we show that the proposed solution significantly improves the encoding robustness to hardware faults.

This paper introduces a new theoretical framework, akin to the use of imprecise message storage in Low Density Parity Check (LDPC) decoders, which is seen as an enabler for cost-effective hardware designs. The proposed framework is the one of Non-Surjective Finite Alphabet Iterative Decoders (NS-FAIDs), and it is shown to provide a unified approach for several designs previously proposed in the literature. NS-FAIDs are optimized by density evolution for WiMAX irregular LDPC codes and we show they provide different trade-offs between hardware complexity and decoding performance. In particular, we derive a set of 27 NS-FAIDs that provide decoding gains up to 0.36 dB, while yielding a memory/interconnect reduction up to 25%/30% compared to the Min-Sum decoder.

Recent work have shown that Reed-Müller (RM) codes achieve the erasure channel capacity. However, this performance is obtained with maximum-likelihood decoding which can be costly for practical applications. In this paper, we propose an encoding/decoding scheme for Reed-Müller codes on the packet erasure channel based on Plotkin construction. We present several improvements over the generic decoding. They allow, for a light cost, to compete with maximum-likelihood decoding performance, especially on high-rate codes, while significantly outperforming it in terms of speed.

Gold sequences are widely used in communications and positioning systems for synchronization purposes or spread spectrum transmissions. This paper addresses the decoding of the initial state of a Gold sequence. This can be used to detect a harmful interferer closed to a 3G femtocell base station and implement interference mitigation techniques. The decoder implements an iterative message-passing algorithm which is built upon a parity check matrix. Thus, it depends on the coding properties of Gold codes. In this paper, we synthesize the coding properties of Gold codes and use them to compute the number of parity check equations of weight t = 3, 4 or 5. Eventually, the impact of the parity check equations used for decoding is highlighted.

This paper focuses on the practical implementation of a Cloud-RAN architecture in the context of future 5G systems, with particular emphasis on different aspects of the functional split between the cloud platform and the radio access points. First, we provide a comprehensive overview of implementation aspects and how different hardware options impact the implementation of RAN functionality. We further discuss a virtualized infrastructure which may have a significant impact on how algorithms are implemented, how they interact with each other, and how they can be scaled within the RAN. We also analyze implementation constraints to be considered to provide backwards compatibility with 3GPP LTE; such constraints on the computing platforms result from the RAN requirements in terms of latency and throughput. Finally, the level of flexibility achievable by the proposed architecture is described from a practical point of view.

This paper addresses the problem of designing low-density parity check decoders robust to transient errors introduced by faulty hardware. We assume that the faulty hardware introduces errors during the message-passing updates, and we propose a general framework for the definition of the message update faulty functions. Within this framework, we define symmetry conditions for the faulty functions and derive two simple error models used in the analysis. With this analysis, we propose a new interpretation of the functional density evolution threshold introduced by Kameni et al. in the recent literature and show its limitations in the case of highly unreliable hardware. However, we show that under restricted decoder noise conditions, the functional threshold can be used to predict the convergence behavior of finite alphabet iterative decoders (FAIDs) under faulty hardware. In particular, we reveal the existence of robust and nonrobust FAIDs and propose a framework for the design of robust decoders. We finally illustrate robust- and nonrobust-decoder behaviors of finite-length codes using Monte Carlo simulations.

In this paper, we investigate the problem of designing good non-binary LDPC codes for Slepian-Wolf coding. The design method is based on Density Evolution which gives the asymptotic error probability of the decoder for given code degree distributions. Density Evolution was originally introduced for channel coding under the assumption that the channel is symmetric. In Slepian-Wolf coding, the correlation channel is not necessarily symmetric and the source distribution has to be taken into account. In this paper, we express the non-binary Density Evolution recursion for Slepian-Wolf coding. From Density Evolution, we then perform code degree distribution optimization using an optimization algorithm called differential evolution. Both asymptotic performance evaluation and finite-length simulations show the gain at considering optimized degree distributions for SW coding.

This paper investigates the behavior of the Min-Sum decoder running on noisy devices. Our aim is to evaluate the robustness of the decoder to computation noise caused by the faulty logic in the processing units. This type of noise represents a new source of errors that may occur during the decoding process. To this end, we first introduce probabilistic models for the arithmetic and logic units of the finite-precision min-sum decoder and then carry out the density evolution analysis of the noisy min-sum decoder. We show that, in some particular cases, the noise introduced by the device can help the min-sum decoder to escape from fixed points attractors and may actually result in an increased correction capacity with respect to the noiseless decoder. We also point out a specific threshold phenomenon, referred to as functional threshold, which accurately describes the convergence behavior of noisy decoders. The behavior of the noisy MS is demonstrated in the asymptotic limit of the code length through a noisy version of density evolution and is also verified in the finite-length case by Monte Carlo simulations.

This paper proposes an FPGA based layered architecture for quasi-cyclic (QC) irregular LDPC decoder. Our approach is based on merging variable and check node processing into one single variable-check node (VCN) unit. Layer message computation is done using a parallel scheme of a number of VCNs equal to the expansion factor of the QC matrix. The proposed architecture is characterized by the serial processing of the a posteriori LLRs by an FPGA specific high frequency VCN unit implementation using ROM memories. In our approach data conversions as well as additions and comparators are replaced by look-up-tables implemented using distributed RAM. In addition to this, other techniques such as: efficient packaging of LLRs messages and check-node message compression as well as the configurable port width of the FPGA's BRAM are used to reduce BRAM block utilization. Throughput increase is achieved by utilizing techniques such as pipelining, parallel processing of multiple VCNs, as well as relatively high working frequency. Implementation results for the WiMAX (1152, 2304) QC irregular LDPC code indicate that the proposed architecture has up to 3x less slices resource utilization and up to 1 order of magnitude less BRAM blocks with respect to other approaches, while maintaining a throughput of several hundreds of Mbps (800 Mbps coded bits). We achieved this without sacrificing flexibility; therefore we can easily adapt our design to accommodate different code rates.

This paper deals with Low-Density Parity-Check decoders running on noisy hardware. This represents an unconventional paradigm in communication theory, since it is traditionally assumed that the error correction decoder operates on error-free devices and the randomness (in the form of noise and/or errors) exists only in the transmission channel. However, with the advent of nanoelectronics, it starts to be widely accepted that the future generations of circuits and systems will need to reliability compute and solve statistical inferences, by making use of unreliable “noisy” components. It is then critical to properly evaluate the robustness of the existing decoders in the presence of an additional source of noise at the circuit level. To this end, we first introduce a new error model approach and carry out the “noisy” density evolution analysis of the fixed-point Min-Sum decoding. Then, for different parameters of the noisy components of the decoder, we determine the range of the signal-to-noise ratio values for which the decoder is able to achieve a target bit error rate performance. Finally, we evaluate the finite-length performance of the Min-Sum and two other Min-Sum-based decoders running on noisy hardware.

The tradeoff between error-correcting performance and numerical complexity of LDPC decoding algorithms is a well-known problem. In this paper we depict the unseen error-floor performance of the Self-Corrected Min-Sum algorithm for long length DVB-S2 codes. We developed a massively parallel simulation using GPUs which allowed a comprehensive BER characterization either in the waterfall or in the error-floor region. We show that the self-correction technique increases the BER performance by 0.5 and 0.2 dB, in the waterfall and error-floor region, when compared to the Min-Sum algorithm. Furthermore, it reaches within 0.2 dB to the Logarithmic Sum-Product BER performance and it also outperforms the Normalized Min-Sum at high SNR, a low complexity decoding algorithm which yields good BER performance.

Interference between macro and femtocells is an important issue for the development of WCDMA femtocell networks. More specifically, the uplink signal of a macro User Equipment may generate an unacceptable level of interference at the femto Base Station. To avoid this situation, interference mitigation techniques could be implemented. All the proposed techniques require the knowledge of the uplink scrambling code index of the interferer. Unfortunately, if the femto BS is in a closed access mode, there are no signalling links with the surrounding macro BSs. The femto BS has to estimate blindly this scrambling code index. An algorithm which performs a blind identification of the uplink scrambling code index of a WCDMA transmission is proposed in this article. This gives the possibility to implement interference cancelation algorithm at the femto BS.

Interference between macro and femtocells is an important issue for the development of CDMA2000 femtocell networks. More specifically, the reverse link signal of a macro User Equipment may generate an unacceptable level of interference at the femto Base Station. To avoid this situation, interference mitigation techniques could be implemented. All the proposed techniques require to know the state of the scrambling code of the interferer in the reverse link. Unfortunately, it depends on the code mask of the terminal which is unknown by the femto BS. The femto BS has to estimate blindly the state of the scrambling code. An algorithm which performs a blind identification of the scrambling code of a CDMA2000 reverse link transmission is proposed in this article. This gives the possibility to implement interference cancelation algorithm at the femto BS.

This paper considers heterogeneous cellular networks, where cluster of small cells are deployed to create local hot spots inside the macro cell. In the past, most of the research in this topic has focused on mitigating inter cell interference; however, wireless backhaul has recently emerged as an urgent challenge to enable ubiquitous broadband wireless services at small cells. Hence, we propose a novel cell selection framework, which associates users and heterogeneous access nodes to improve the efficiency in the overall radio and backhaul resource utilization and avoid load congestions. We also model the relationships amongst cell load, resource management, backhaul capacity constraints, and the overall network capacity. Then, we describe the cell selection problem and we present a heuristic algorithm, named as Evolve, to solve it with limited complexity. Our analysis shows that Evolve achieves near optimal performance leading to notable capacity improvements with respect to the classic SINR based association scheme.

This paper continues a previous work on non-binary cluster-LDPC codes. Such codes are defined by locally dense parity-check matrices, with (possibly rectangular) dense clusters of bits, but which are cluster-wise sparse. We derive a lower bound on the minimum distance of non-binary cluster-LDPC codes that is based on the topological properties of the underlying bipartite graph. We also propose an optimization procedure, which allows designing finite length codes with large minimum distance, even in the extreme case of codes defined by ultra-sparse graphs, i.e. graphs with all symbol-nodes of degree dv= 2. Furthermore, we provide asymptotic thresholds of ensembles of non-binary cluster-LDPC codes, which are computed exactly under the Belief Propagation decoding, and upper-bounded under the Maximum a Posteriori (MAP) decoding. We show that the MAP-threshold upper bounds, which are conjunctured to be tight, quickly approach the channel capacity, which confirms the excellent minimal distance properties of non-binary cluster-LDPC codes.

In this paper we propose a binary representation of non-binary codes, which consists in a q-fold covering of the non-binary graph, where q is the size of the non-binary alphabet. It is shown that this covering graph is actually the underlying graph of the Fourier-domain Belief-Propagation decoding, meaning that the exchanged messages carry information about the bit-nodes of the covering graph. Finally, a new coding scheme is proposed, in which the bits transmitted over the channel correspond to a set of bit-nodes of the Fourier domain representation. The proposed coding scheme allows using the same decoder, regardless of how many and which of the Fourier-domain bit-nodes have been transmitted. This considerably increases the flexibility of the system, without increasing its complexity.

In this paper we analyze the performance of several bit-interleaving strategies applied to Non-Binary Low-Density Parity-Check (LDPC) codes over the Rayleigh fading channel. The technique of bit-interleaving used over fading channel introduces diversity which could provide important gains in terms of frame error probability and detection. This paper demonstrates the importance of the way of implementing the bit-interleaving, and proposes a design of an optimized bit-interleaver inspired from the Progressive Edge Growth algorithm. This optimization algorithm depends on the topological structure of a given LDPC code and can also be applied to any degree distribution and code realization. In particular, we focus on non-binary LDPC codes based on graph with constant symbol-node connection dv= 2. These regular (2, dc)-NB-LDPC codes demonstrate best performance, thanks to their large girths and improved decoding thresholds growing with the order of Finite Field. Simulations show excellent results of the proposed interleaving technique compared to the random interleaver as well as to the system without interleaver.

In this paper, we study the asymptotic minimum distance of non-binary cluster-LDPC codes whose subjacent binary parity-check matrix is composed of localized density of ones, concentrated in clusters of bits. A particular attention is given to cluster codes represented by ultra-sparse bipartite graphs, in the sense that each symbol-node is connected to exactly dv= 2 constraint-nodes. We derive a lower bound on the minimum distance of non-binary cluster-LDPC codes and we show that there exist ensembles of ultra-sparse codes whose minimum distance grows linearly with the code length (with probability going to 1 as the code length goes to infinity). This result is in contrast with “classical” non-binary LDPC codes based on graphs with strictly regular dv= 2 symbol-nodes, whose minimum distance grows at most logarithmically with the code length. We also show that one can build practical non-binary cluster-LDPC codes with various finite codeword lengths, whose minimum distance is close to the Gilbert-Varshamov bound.

In this paper, we show that over the binary erasure channel, Quasi-Cyclic LDPC codes can efficiently accommodate the hybrid iterative/ML decoding. We demonstrate that the quasi-cyclic structure of the parity-check matrix can be advantageously used in order to significantly reduce the complexity of the ML decoding. This is achieved by a simple row/column permutation that transforms a QC matrix into a pseudo-band form. Based on this approach, we propose a class of QC-LDPC codes with almost ideal error correction performance under the ML decoding, while the required number of row/symbol operations scales as k√k, where k is the number of source symbols.

In this paper we design non-uniform bit-wise puncturing distributions for irregular non-binary LDPC (NB-LDPC) codes. The puncturing distributions are optimized by minimizing the decoding threshold of the punctured LDPC code, the threshold being computed with a Monte-Carlo implementation of Density Evolution. First, we show that Density Evolution computed with Monte-Carlo simulations provides accurate (very close) and precise (small variance) estimates of NB-LDPC code ensemble thresholds. Based on the proposed method, we analyze several puncturing distributions for regular and semi-regular codes, obtained either by clustering punctured bits, or spreading them over the symbol-nodes of the Tanner graph. Finally, optimized puncturing distributions for non-binary LDPC codes with small maximum degree are presented, which exhibit a gap between 0.2 and 0.5 dB to the channel capacity, for punctured rates varying from 0.5 to 0.9.

We propose a new code design that aims to distribute an LDPC code over a relay channel. It is based on a split-and-extend approach, which allows the relay to split the set of bits connected to some parity-check of the LDPC code into two or several subsets. Subsequently, the sums of bits within each subset are used in a repeat-accumulate manner in order to generate extra bits sent from the relay toward the destination. We show that the proposed design yields LDPC codes with enhanced correction capacity and can be advantageously applied to existing codes, which allows for addressing cooperation issues for evolving standards. Finally, we derive density evolution equations for the proposed design, and we show that Split-Extended LDPC codes can approach very closely the capacity of the Gaussian relay channel.

In this paper, we propose a class of irregular turbo codes that approach the capacity of the binary erasure channel. First, an analytic expression of the erasure probability of punctured recursive systematic convolutional codes is derived. This expression will then be used to study the density evolution of turbo codes over the binary erasure channel, that will allow for the design of capacity-approaching infinite-length irregular turbo codes. Next, a graph-optimal interleaver for finite-length irregular turbo codes is proposed. Finally, simulation results for different coding rates are shown.

In this paper we propose a very simple but powerful self-correction method for the min-sum decoding of LPDC codes. Unlike other correction methods known in the literature, our method does not try to correct the check node processing approximation, but it modifies the variable node processing by erasing unreliable messages. However, this positively affects check node messages, which become symmetric Gaussian distributed, and we show that this is sufficient to ensure a quasi-optimal decoding performance. Monte-Carlo simulations show that the proposed self-corrected min-sum decoding performs very close to the sum-product decoding, while preserving the main features of the min-sum decoding, that is low complexity and independence with respect to noise variance estimation errors.

Iterative decoding of non-binary LDPC codes is currently performed using either the sum-product or the min-sum algorithms or slightly different versions of them. In this paper, several low-complexity quasi-optimal iterative algorithms are proposed for decoding non-binary codes. The min-max algorithm is one of them and it has the benefit of two possible LLR domain implementations: a standard implementation, whose complexity scales as the square of the Galois field's cardinality and a reduced complexity implementation called selective implementation, which makes the min-max decoding very attractive for practical purposes.

In this paper we study the impact of the processing order of nodes of a bipartite graph, on the performance of an iterative message-passing decoding. To this end, we introduce the concept of neighborhood reliabilities of graph's nodes. Nodes reliabilities are calculated at each iteration and then are used to obtain a processing order within a serial or serial/parallel scheduling. The basic idea is that by processing first the most reliable data, the decoder is reinforced before processing the less reliable one. Using neighborhood reliabilities, the min-sum decoder of LDPC codes approaches the performance of the sum-product decoder.