Implantable Medical Devices (IMDs) have emerged as healthcare assets, profoundly enhancing patients’ quality of life. Although wireless communication in remotely monitored IMDs emphasises its functionalities, it leaves them vulnerable to various security threats. The resource-constrained IMD environment and their unfamiliar access requirements during device or patient emergencies make the adoption of traditional security approaches impractical in this domain. The prevalence of cardiac diseases worldwide has made implantable cardioverter defibrillators (ICDs) one of the most popular IMDs with cutting-edge connectivity and functions. In this paper, we identify the data manipulation attack on ICDs as the most life-threatening attack, which involves the use of malicious clinical programmer. A possible command modification attack scenario is presented which exploits ICDs’ legitimate functionalities. This will assist in developing countermeasures for the identified attack to provide a secure ICD environment.

The authors explore a cryptanalysis strategy which seems to be particularly applicable to parallelisable ciphers where the key forms a part of the internal state. The proposed technique combines internal differentials with guess and determine analysis to come up with what is referred to as the match‐in‐the‐end attack. The notion of difference here deviates from the classical differential where the difference is controllable via the plaintext/ciphertext. Here, they exploit the Hamming distance between parallel branches to devise the differential trail. They apply the strategy on full eight (out of 20) rounds of parallelisable authenticated cipher [parallelisable AE based on quadrupled AES ( PAEQ )] to devise key recovery attacks with practical time complexities. They first show an initial attack on paeq‐64/80/128 and then devise improvements which give us the best key‐recovery attacks with time complexities of , and , respectively. While the best reported attacks on eight‐round paeq‐64/80/128 have a data complexity of blocks, the result improves their time complexities by factors of , and , while preserving the data complexity. Finally, they present a nonce‐based differential attack which works on paeq‐128‐t with time complexity but uses just two single block known plaintexts making it the most practical attack on any round‐reduced PAEQ variant reported so far.

This paper proposes a continuous authentication scheme for use in remote monitored biomedical devices, such as the Implantable Cardioverter Defibrillator or for a Pacemaker. In the age of remote monitoring, all your heart data is readily available on the device and is accessible to the doctor over the internet. However, it is possible that in the logged-in state and with the computer left unattended, someone else tries to access your data, or modify the ICD/Pacemaker settings, or perhaps (in future applications) even try to instruct a biomedical device to send a shock to your heart when it was not required. While the first two intrude privacy, the third could be potentially lethal - hence it is not currently in use due to security concerns. The scheme proposed in this paper protects the privacy of the user in the previous two cases, allows for the expansion of the remote monitoring realm to allow for the third case, and also deals with channel attacks, in which instructions or data is modified by an adversary over the channel.

This paper presents a differential fault analysis of the MICKEY-128 2.0 stream cipher, one of the finalist of eStream project. The current attack works on MICKEY-128 2.0 with 320 state register-bits and requires 480 number of random single bit faults to break it. Till date, only two fault attacks against MICKEY family are available in literature, one attack on MICKEY-128 and another on MICKEY 2.0. The attack on MICKEY-128 with same 320 register bits required 640 number of faults whereas the other attack on MICKEY 2.0 with 200 state register bits required $2^{16.7} number of faults. To the best of our knowledge the current attack gives the best performance with respect to the number of faults to be induced against the highest version of MICKEY, MICKEY-128 2.0.

This paper is devoted to the design and the physical security of a parallel dual-core flexible cryptoprocessor for computing pairings over Barreto-Naehrig (BN) curves. The proposed design is specifically optimized for field-programmable gate-array (FPGA) platforms. The design explores the in-built features of an FPGA device for achieving an efficient cryptoprocessor for computing 128-bit secure pairings. The work further pinpoints the vulnerability of those pairing computations against side-channel attacks and demonstrates experimentally that power consumptions of such devices can be used to attack these ciphers. Finally, we suggest a suitable countermeasure to overcome the respective weaknesses. The proposed secure cryptoprocessor needs 1 730 000, 1 206 000, and 821 000 cycles for the computation of Tate, ate, and optimal-ate pairings, respectively. The implementation results on a Virtex-6 FPGA device shows that it consumes 23 k Slices and computes the respective pairings in 11.93, 8.32, and 5.66 ms.

We present a scalable, modular, memoryless, and reconfigurable parallel architecture to generate cryptographically robust mappings, which are useful in the construction of stream and block ciphers. It has been theoretically proved that the proposed architecture can be reconfigured to generate a large number of mappings, all of which have high nonlinearity, satisfies Strict Avalanche Criterion (SAC) and is robust against linear and differential cryptanalysis. The architecture can be also used to optimize the resiliency and algebraic degree. The architecture has been found to scale easily to handle large number of input variables, which is an important criterion in realizing nonlinear combiners for stream ciphers using Boolean functions.

Cellular automata (CA) has already established its novelty for bits and bytes error correcting codes (ECC). The current work identifies weakness and limitation of existing CA-based byte ECC and proposes an improved CA-based double byte ECC which overcomes the identified weakness. The code is very much suited from VLSI design viewpoint and requires significantly less hardware and power for decoding compared to the existing techniques employed for Reed-Solomon (RS) Codes. Also it has been shown that the CA-based scheme can easily be extended for correcting more than two byte errors.

The seed (initial state) of a pseudo-random pattern generator (PRPG) for built-in self-test (BIST), significantly influences the fault coverage and total test application time. This paper introduces a one-pass seed selection algorithm, for any known PRPG. Due to its single-pass nature, unlike the state-of-the-art exhaustive search methods, the proposed algorithm is more time and memory efficient. Experimental results on ISCAS'85 and ISCAS'89 benchmark circuits, and synthetic SoCs built out of the combinational benchmarks, show considerable reduction in test length within comparable fault efficiencies, almost 100%, with respect to the existing methods.

The high complexity and the core diversities make timing verification of an entire flattened SoC design a tedious process. In this paper, at first the various timing issues related to modular SoC verification have been investigated and then a bottom-up hierarchical approach of verifying the system level timing of an SoC, is presented. The timing abstractions of the cores are assumed to be provided by the core vendors. The interconnection delays of the SoC may be extracted from the SDF file generated after post layout simulation. The hierarchical approach provides a fast and systematic way of timing verification, as opposed to the flattened approach. Experiments were conducted on synthetic SoCs, using ISCAS benchmark circuits as cores. Results validate the claim of the proposed approach.

Masking of gates is one of the most popular techniques to prevent differential power analysis (DPA) of AES algorithm. It has been shown that the logic circuits used in the implementation of cryptographic algorithms leak side-channel information inspite of masking, which can be exploited, in differential power attacks. The phenomenon in CMOS circuits responsible for the leakage of masked circuits is known as glitching. Motivated by this fact, the authors analyse the effect of glitches in CMOS circuits against masked implementation of the AES S-box. The authors explicitly demonstrate that glitches do not affect always. There exists a relation between combinational path delay of the circuit and timing difference of input vectors to the circuit, which has a bearance on the amount of information leaked by the masked gates. A balanced masked S-box circuit is proposed where the inputs are synchronised by sequential components. Detailed SPICE results are shown to support the claim that the modifications indeed reduce the vulnerability of the masked AES S-box against DPA attacks.

This paper deals with FPGA and ASIC implementations of side-channel attack resistant elliptic curve cryptosystems defined over GF(p). The elegance of the design lies in the fact that all operations are performed in binary number system, thus reducing conversion overheads of existing architectures. In our implementation, point addition and point doubling operations are performed in affine coordinates. They are performed using same amount of computation, which provides a secure design against timing and power analysis attacks. Implementation and side-channel analysis results are compared with related existing designs.

This paper presents the architecture and FPGA implementation of a robust GF(p) parallel arithmetic unit. The most efficient modular multiplication, inversion and division units greatly reduce the clock cycles requirement for point operations applicable to elliptic curve cryptography. The parallel arithmetic unit helps to achieve a high speed up in cryptographic applications. The architecture can resist the cryptographic timing attack. Integrated input and output interface units provide lower bandwidth requirement to plug in the architecture with automated cryptographic systems. The design exhibits its elegance among competitive architecture with respect to throughput and robustness.

Tree-based scan path architectures have recently been suggested for reducing test application time or test data volume in today's high-density very large scale integrated circuits. However, these techniques strongly rely on the existence of a large number of compatible sets of flip-flops under the given test set and therefore may not be suitable for a highly compact test set generated by an efficient automatic test pattern generator tool. Tree-based architectures also suffer from loss of fault coverage while achieving a significant reduction ratio for test time or data. In this paper, to circumvent this problem, a new two-pass hybrid method is proposed to design an efficient scan tree architecture based on approximate compatibility. The method is particularly suitable for a highly compact test set having fewer don't cares and low compatibility. Finally, to reduce the volume of scan-out data, test responses shifted out from the leaf nodes of the scan tree are compacted by a space compactor, which is designed specially for the proposed scan tree architecture. The compactor uses an XOR tree, and its overhead is low. The design thus offers a solution to both test data and response compaction. Experimental results on various benchmark circuits demonstrate that the proposed algorithm outperforms the earlier methods in reducing test application time significantly without degrading fault coverage.

This paper proposes a hierarchical method for the formal hardware verification of Galois field architecture circuits. The reduced ordered functional decision diagram has been explored. The proposed method has been found to lead to significant gains in time and space, depending on the resources that are available. The theoretical claims that were made have been supported by experiments.

Scan chains are exploited to develop attacks on cryptographic hardware and steal intellectual properties from the chip. This paper proposes a secured strategy to test designs by inserting a certain number of inverters between randomly selected scan cells. The security of the scheme has been analyzed. Two detailed case studies of RC4 stream cipher and AES block cipher have been presented to show that the proposed strategy prevents existing scan-based attacks in the literature. The elegance of the scheme lies in its less hardware overhead.

Cellular automaton (CA) has been shown to be capable of generating complex and random patterns out of simple rules. There has been constant efforts of applying CA to develop ciphers, but the attempts have not been successful. This paper describes how repeated application of simple CA transforms may be used to achieve confusion and diffusion, needed in block ciphers. The components have been evaluated for their robustness against conventional cryptanalysis and the results have been found to be comparable to standards. Finally, the parts are assembled in an unconventional way to construct a self-invertible CA based round, which is resistant against linear and differential cryptanalysis and yet can be efficiently implemented

This paper introduces an efficient implementation of a test access mechanism (TAM) for mixed-signal system-on-chip (MSOC) testing. The design-for-testability (DFT) strategy has been developed to make the testing of analog cores digitally compliant. The mixed-signal cores have been accessed through specially design mechanisms (switches). A computer-aided test (CAT) tool employing the proposed algorithm has been developed. Extensive experiments have been performed on MSOC benchmarks built of ISCAS'89 circuits for digital cores and ITC'97 circuits for analog cores. Results show that the CAT tool provides a hardware-efficient integrated solution.

Scan based testing is a powerful and popular test technique. However the scan chain can be used by an attacker to decipher the cryptogram. The present paper shows such a side-channel attack on LFSR-based stream ciphers using scan chains. The paper subsequently discusses a strategy to build the scan chains in a tree based pattern with a selfchecking compactor. It has been shown that such a structure prevents such scan based attacks but does not compromise on fault coverage.

Abstract — This paper introduces a new design-for-test(DFT) technique for system-on-chip(SOC) designs. It aims to provide the test designer with details of test scheduling, test access mechanism (TAM) design and an integrated test strategy in order to implement an efficient test solution. Post-synthesis simulations are carried out on the net lists of ISCAS’89 benchmark SOCs to prove the allegiance of the proposed algorithm and to realize the DFT. Experiments resulted in a significant reduction of the test time. I.

This paper extends the theory of autonomous linear machines (LMs). The theory of the extension field has provided the foundation for the design of such machines referred to as Extended Linear Machines (ELM). An analytical framework has been reported to completely characterize the vector subspace generated by an ELM and also different variations of LMs having cyclic, as well as noncyclic vector subspaces. This formulation has resulted in a single algorithm that characterizes each of the vector subspaces in terms of cyclic and noncyclic subspaces. An ELM significantly reduces the computation time for characterizing the model and study of the behavior of the physical system compared to conventional binary linear machines.

A novel scheme for board level fault diagnosis based on cellular automata array (CAA) is presented. In the proposed diagnosis scheme, the output responses of the chips are encoded by applying the strategy of CA-based byte error correcting code. The encoded response symbols for different test vectors are compressed to a signature. The decoding scheme of byte error correcting code is subsequently employed to detect the faulty chips on the board. The CAA-based design for the fault diagnosis strategy results in a simple and modular test structure that is well suited for VLSI implementation. The scheme can be applied for testing and diagnosis of multichip modules (MCMs) as well.

Analytical study of three neighbourhood two state per cell Cellular Automata (CA) behaviour is a comparatively recent phenomenon. A wide variety of applications have been developed utilizing the elegant structure of group CA. In this paper some of the characterizations of the state transition behaviour of non-group CA are reported. These results are subsequently utilized to develop an efficient parallel scheme for image compression. The experimental results confirms compression ratio of the CA based scheme is of the same order as that of JPEG coding.

The paper reports some of the interesting properties and relationships of a nongroup cellular automata (CA) and its dual. A special class of nongroup cellular automata denoted as D1*CA is analytically investigated. Based on such analysis, D1*CA has been proposed as an ideal test machine which can be efficiently embedded in a finite state machine to enhance the testability of the synthesized design. A state encoding algorithm has been formulated to embed the D1*CA based test machine in the synthesized FSM while minimizing the hardware overhead. The unique state transition properties of D1*CA are then used in designing an easy testing scheme for the FSM. Experiments on FSM benchmarks have shown that the scheme achieves 100% coverage of all single stuck at faults at the cost of hardware overhead and circuit delay that are comparable, if not better, to that incurred for scan path based designs. However, the major advantage of the scheme is the significant reduction of test time overhead due to integration of an embedded test machine in the design at the synthesis phase.

The present paper reports a novel scheme for designing fast retrieval memory system using cellular automata. In essence, the proposed scheme implements the concept of hashing in hardware. This makes possible the design of low-cost high-capacity memory systems with limited content addressability as an option. The efficiency of the scheme has been verified through extensive simulation studies of the hardwired hashing function built around 1D and 2D linear cellular automata (CA).>

This paper reports a novel approach for designing byte error-correcting codes using cellular automata (CA). A simple scheme for generation and decoding of single-byte error-correcting and double-byte error-detecting codes, referred to as CA-SbEC-DbED, is presented. Extension of the scheme to locate/correct larger number of information byte errors has been also included. The encoding and decoding algorithms have been designed with the help of a linear operator that can be conveniently realized with a maximum length group CA. The regular, modular and cascadable structure of CA can be economically built with VLSI technology. Compared to the existing architecture of the Reed-Solomon decoder chip, CA-based implementation of the proposed decoding scheme provides a simple cost effective solution.>

A new scheme for designing error detecting and error correcting codes around cellular automata (CA) is reported. A simple and efficient scheme for generating SEC-DED codes is presented which can also be extended for generating codes with higher distances. A CA-based hardware scheme for very fast decoding (and correcting) of the codewords is also reported.>

The paper reports an application of a special class of non-group cellular automata, referred to as D1/sup */CA, as the test machine embedded in the FSM to be synthesized. The state transition properties of D1/sup */CA are exploited in designing an easy testing scheme for the finite state machine. The scheme has been found to incur a small area overhead while providing extremely high coverages close to 100% for all single stuck-at faults in the circuit.