Demo Data from VLDB 2026 / reviewers in the wild / expert
John W. Jones III
dblp:09/6986
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1980
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Processor architecture and microarchitecture · 40% Electronic design automation · 20% Embedded and real-time systems · 20% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Embedded and real-time systems › real-time scheduling
deterministic scheduling |
0.0 | 1 | 1980 | Deterministic Scheduling with Pipelined Processors · IEEE Trans. Computers 1980 |
Processor architecture and microarchitecture › pipelining
pipelined processor |
0.0 | 1 | 1980 | Deterministic Scheduling with Pipelined Processors · IEEE Trans. Computers 1980 |
Processor architecture and microarchitecture › instruction scheduling
pipelined processor scheduling |
0.0 | 1 | 1980 | Deterministic Scheduling with Pipelined Processors · IEEE Trans. Computers 1980 |
Electronic design automation › high-level synthesis
scheduling |
0.0 | 1 | 1980 | Deterministic Scheduling with Pipelined Processors · IEEE Trans. Computers 1980 |
Parallel and multicore computing
task scheduling |
0.0 | 1 | 1980 | Deterministic Scheduling with Pipelined Processors · IEEE Trans. Computers 1980 |
Methods — techniques the papers use, named apart from their topics
precedence constraint analysis · 0.0coffman-graham algorithm · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1980 | Deterministic Scheduling with Pipelined ProcessorsabstractIn this paper several results are proven showing a correspondence between problems involving task systems with single-stage processors and similar ones using pipelined processors. For example, an optimal schedule for a task system with arbitrary precedence constraints using a single pipelined processor with two stages is found by the familiar Coffman–Graham algorithm for a system with two single-stage processors. Precedence constraints in the form of inforests, out-forests, and directed acyclic graphs are examined. Task systems with release times and deadlines for each task are also considered. John L. Bruno, John W. Jones III, Kimming So |
IEEE Trans. Computers | 2 |