The integration of strong security functionality to radio-frequency identification (RFID) tags operating in the ultra-high frequency (UHF) range is challenging. Main limiting factors are chip size and power consumption. In this work we present the design of the digital part of a security-enhanced UHF RFID tag that uses the Electronic Product Code (EPC) Generation-2 (Gen-2) standard for communication. The tag provides mutual-authentication functionality based on a challenge-response protocol and the Advanced Encryption Standard (AES). The stream cipher Grain is used for generating cryptographically secure random numbers during the authentication procedure. Moreover, the AES module on the tag has countermeasures integrated (shuffling of bytes and insertion of dummy rounds) to make so-called power analysis attacks less efficient. The digital part of the security-enhanced tag including AES and Grain modules can be implemented with 12000 GE (without non-volatile memory). The average power consumption during a full authentication round is 5 uW for a 130 nm low-leakage technology. The results clearly point out that both values chip size and power consumption fulfill the requirements of low-cost UHF RFID tags.

Cryptographic hash functions are used to protect information integrity and authenticity in a wide range of applications. After the discovery of weaknesses in the current deployed standards, the U.S. Institute of Standards and Technology started a public competition to develop the future standard SHA-3, which will be implemented in a multitude of environments, after its selection in 2012. In this paper, we investigate high-speed and low-area hardware architectures of one of the 14 “second-round” candidates in this competition: BLAKE. VLSI performance results of the proposed high-speed designs indicate a throughput improvement between 16% and 36% compared to the current standard SHA-2. Additionally, we propose a compact implementation of BLAKE with memory optimization that fits in 0.127 mm2of a 0.18 μ m CMOS. Measurements reveal a minimal power dissipation of 9.59 μW/MHz at 0.65 V, which suggests that BLAKE is suitable for resource-limited systems.

In the next years, new hash function candidates will replace the old MD5 and SHA-1 standards and the current SHA-2 family. The hash algorithms RadioGatun and irRUPT are potential successors based on a stream structure, which allows the achievement of high throughputs (particularly with long input messages) with minimal area occupation. In this paper, several hardware architectures of the two above mentioned hash algorithms have been investigated. The implementation on ASIC of RadioGatun with a word length of 64 bits shows a complexity of 46 k gate equivalents (GE) and reaches 5.7 Gbps throughput with a 3.64-bit input message. The same design approaches 120 Gbps on ASIC with long input messages (63.4 Gbps on a Virtex-4 FPGA with 2.9 kSlices). On the other hand, the irRUPT core turns out to be the most compact circuit (only 5.8 kGE on ASIC, and 370 Slices on FPGA) achieving 2.4 Gbps (with long input messages) on ASIC, and 1.1 Gbps on FPGA.

A public competition organized by the NIST recently started, with the aim of identifying a new standard for cryptographic hashing (SHA-3). Besides a high security level, candidate algorithms should show good performance on various platforms. While an average performance on high-end processors is generally not critical, implementability and flexibility in hardware is crucial, because the new standard will be implemented in a variety of lightweight devices. This paper investigates VLSI architectures of the SHA-3 candidates MD6 and irRUPT. The fastest circuit is the 16timesparallel MD6 core, reaching 16.3 Gbps at a complexity of 69.8 k gate equivalents (GE) on ASIC and 8.4 Gbps using 4465 Slices on FPGA. However, large memory requirements preclude the application of MD6 to resource-constrained systems. The most flexible and efficient circuit turns out to be our 2-irRUPT64times2-256/8 core, which achieves a throughput of 5.0 Gbps at 12.7 kGE on ASIC and 1.7 Gbps using 613 Slices on FPGA.

Eleven latch circuits for ultra-low-power applications with resonant clocking are compared in terms of energy dissipation (the main focus of this work), propagation delay, set-up, and hold time in a wide range of operating frequencies and supply voltages. Transistor-level simulations in a 0.18 µm process point out that the ratioless circuit Cut Cross-over current latch (CC-Latch) saves up to 15% energy towards the second best competitor in low- to mid-frequency applications. The improved efficiency is due to the suppression of the excess of cross-over current, by switching of the pull-up or the pull-down network alternatively in the forward inverter of the latch.