Analog and Mixed Signal circuit sizing with large-scale parameters requires a lot of simulations, especially in non-linear topology where large-signal analysis is a need. Reducing the number of simulations and in general the total design cycle time, is the main objective for optimal sizing of complicated circuits. In this work a circuit sizing automated design methodology is presented using the hybrid dual annealing and Nelder–Mead algorithm, significantly reducing the design cycle time and the required number of transient simulations. A customized hybrid algorithm environment using Dual Annealing and Nelder–Mead is developed where the optimization process is divided into different optimization sub-steps. The proposed hybrid algorithm based method achieves rapid convergence to the needed circuit performance specification. It uses combinations of direct search algorithms to separate metric evaluation accelerating the performance specifications convergence speed in a large parameter space. A complicated non-linear topology like a product level low-dropout (LDO) regulator, in 180 nm process node, with 30 parameters is used as the circuit vehicle to verify the proposed methodology. The sizing process converged with less than 1700 simulations having as input just the circuit schematic with no prior sizing knowledge. Sub optimization is also performed focused on each analysis type - DC, AC and transient, with a focus on reducing the number of transient simulations. The proposed combined algorithm method achieved 31 % faster convergence speed compared to the state-of-the-art methods and handles efficiently each simulation analysis. • Analog circuits have metrics that in general need different simulation types for evaluation. A number of combinations of algorithms are proposed to optimize different sub-stages of the process. • A large LDO circuit is used as a base for the demonstration and comparison of the methodologies, with 30 parameters and 10 performance metrics. • Significant number of transient analysis simulations is reduced (31%), keeping the result within the error limits, using the best performing hybrid algorithms that include Nelder–Mead, Dual Annealing, NSGA-II, etc.

Reliable millimeter-wave frequency synthesis requires oscillator designs that combine wide tuning coverage, low phase noise, and stable operation over broad frequency spans. This work introduces a machine-learning-driven framework for the automated design of LC Digitally Controlled Oscillators (DCOs) covering the 5–30 GHz range in 22-nm FDSOI technology. Surrogate models based on gradient-boosted ensembles are trained to predict oscillation frequency and phase noise directly from device dimensions, tank parameters, and bias conditions, enabling efficient navigation of the multi-dimensional design space. A targeted data-augmentation strategy enhances model generalization throughout the entire operating spectrum, while a frequency-aware decomposition further improves accuracy across the full range of synthesized oscillators. The proposed synthesis algorithm translates user-defined specifications, such as center frequency, tuning range, and phase-noise limits, into feasible transistor-level parameter sets and reconstructs the corresponding tuning boundaries via calibrated tank-capacitance adjustment. The automatically generated designs exhibit strong agreement with schematic and post-layout simulations, achieving wide tuning coverage and competitive phase noise with minimal deviation from predicted values. The results demonstrate that data-driven modeling supports reproducible, scalable, and specification-centric DCO design, offering a systematic alternative to conventional manual procedures and significantly reducing design effort in millimeter-wave oscillator development.

A novel design methodology, enabling extreme design cycle time speed up of DC - DC power converters, is developed. The concept is based on providing high accuracy post-layout RC parasitics aware results, by replacing complicated large RC netlists with small signal approximation models. Scattering parameters analysis is adopted for “on the fly” performance simulation of the power MOSFET switches' routings, which act as large passive linear networks. The RC parasitics aware back end of line (BEOL) S-parameter model is extracted and seamlessly integrated into the schematic testbench, considering the actual circuit as a black box and therefore actively cutting down the design's netlist size to minimum values. Thus, the DC – DC converter performance degradation, that previously could not be simulated, now is accurately predicted and evaluated while the respective simulation time and the number of design iterations needed from layout (physical design) to the schematic and vice versa, are minimized. The proposed methodology is validated using an Integrated Pulse Width Modulation controlled DC - DC converter product vehicle, for light energy harvesting applications, designed, simulated and fabricated in a 0.18 μm CMOS standard process. Experimental results confirm the accuracy and design cycle speed up effectiveness of the proposed novel IC power converter design methodology.

Advanced noise simulation is performed using linear and periodic state RF-CMOS circuit vehicles. As a linear vehicle, an operation amplifier is designed with two amplification stages while as periodic state, a ring oscillator operating in the high frequency region. The small signal noise analyses and phase noise analyses are benchmarked versus large signal direct time domain noise analysis, in relation to the obtained accuracy, the simulation parameters ruling the accuracy and the needed simulation time. The theoretical background of direct time domain (transient) noise analysis, its implementation and the used simulation model together with simulation time-saving and circuit diagnostics capabilities are addressed. In addition, the respective MOSFET noise sources – thermal, flicker and gate noise – are analyzed per device, versus their contribution and their simulation accuracy for both cases (linear and periodic state). Simulation guidelines for a proper noise behavior extraction are summarized and categorized according to each circuit type.

Machine learning (ML) algorithms are utilized for the implementation of a ML python-based model of dynamic behavior of Power DC – DC converters, for energy harvesting applications. This subfield of artificial intelligence, defined as the capability of a machine to imitate intelligent human behavior, is used to perform complex tasks in a way that is similar to how a designer is implementing nonlinear switching circuits, like a power DC-DC converter. The dynamic behavior of this nonlinear vehicle is simulated with ML, and in particular all the related dynamic characteristics, obtained with large signal time domain simulation, such as dynamic voltage drop – electro migration and time domain operation, are now captured rapidly with a ML approach. The related results are benchmarked versus transistor level simulations, depicting superior accuracy in minimum simulation time.